OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] - Rev 41

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
41 Function changed to logic because of some synthesis warnings. mohor 8115d 14h /dbg_interface/tags/sdram_test_working/rtl/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8129d 14h /dbg_interface/tags/sdram_test_working/rtl/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8130d 15h /dbg_interface/tags/sdram_test_working/rtl/
38 Few outputs for boundary scan chain added. mohor 8143d 13h /dbg_interface/tags/sdram_test_working/rtl/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8143d 17h /dbg_interface/tags/sdram_test_working/rtl/
36 Structure changed. Hooks for jtag chain added. mohor 8147d 13h /dbg_interface/tags/sdram_test_working/rtl/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8177d 16h /dbg_interface/tags/sdram_test_working/rtl/
32 Stupid bug that was entered by previous update fixed. mohor 8178d 14h /dbg_interface/tags/sdram_test_working/rtl/
31 trst synchronization is not needed and was removed. mohor 8178d 15h /dbg_interface/tags/sdram_test_working/rtl/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8189d 20h /dbg_interface/tags/sdram_test_working/rtl/
28 TDO and TDO Enable signal are separated into two signals. mohor 8225d 17h /dbg_interface/tags/sdram_test_working/rtl/
27 Warnings from synthesys tools fixed. mohor 8239d 18h /dbg_interface/tags/sdram_test_working/rtl/
26 Warnings from synthesys tools fixed. mohor 8239d 18h /dbg_interface/tags/sdram_test_working/rtl/
25 trst signal is synchronized to wb_clk_i. mohor 8240d 15h /dbg_interface/tags/sdram_test_working/rtl/
23 Trace disabled by default. mohor 8247d 18h /dbg_interface/tags/sdram_test_working/rtl/
22 Register length fixed. mohor 8247d 18h /dbg_interface/tags/sdram_test_working/rtl/
21 CRC is returned when chain selection data is transmitted. mohor 8248d 14h /dbg_interface/tags/sdram_test_working/rtl/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8249d 17h /dbg_interface/tags/sdram_test_working/rtl/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8261d 18h /dbg_interface/tags/sdram_test_working/rtl/
18 Reset signals are not combined any more. mohor 8264d 03h /dbg_interface/tags/sdram_test_working/rtl/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8287d 16h /dbg_interface/tags/sdram_test_working/rtl/
15 bs_chain_o added. mohor 8289d 17h /dbg_interface/tags/sdram_test_working/rtl/
13 Signal names changed to lowercase. mohor 8290d 18h /dbg_interface/tags/sdram_test_working/rtl/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8291d 18h /dbg_interface/tags/sdram_test_working/rtl/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8312d 14h /dbg_interface/tags/sdram_test_working/rtl/
9 Working version. Few bugs fixed, comments added. mohor 8316d 18h /dbg_interface/tags/sdram_test_working/rtl/
8 Asynchronous set/reset not used in trace any more. mohor 8317d 16h /dbg_interface/tags/sdram_test_working/rtl/
5 Trace fixed. Some registers changed, trace simplified. mohor 8318d 14h /dbg_interface/tags/sdram_test_working/rtl/
2 Initial official release. mohor 8323d 14h /dbg_interface/tags/sdram_test_working/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.