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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 110

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Rev Log message Author Age Path
110 Waiting for "ready" improved. mohor 7484d 06h /dbg_interface/trunk/bench/verilog/
102 New version. mohor 7486d 01h /dbg_interface/trunk/bench/verilog/
101 Almost finished. mohor 7486d 02h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7487d 04h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7488d 08h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7488d 20h /dbg_interface/trunk/bench/verilog/
93 tmp version. mohor 7490d 07h /dbg_interface/trunk/bench/verilog/
92 temp version. mohor 7493d 11h /dbg_interface/trunk/bench/verilog/
91 tmp version. mohor 7494d 06h /dbg_interface/trunk/bench/verilog/
90 tmp version. mohor 7495d 01h /dbg_interface/trunk/bench/verilog/
89 temp4 version. mohor 7496d 07h /dbg_interface/trunk/bench/verilog/
88 temp3 version. mohor 7497d 01h /dbg_interface/trunk/bench/verilog/
87 tmp2 version. mohor 7498d 06h /dbg_interface/trunk/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7511d 04h /dbg_interface/trunk/bench/verilog/
75 Simulation files. mohor 7572d 02h /dbg_interface/trunk/bench/verilog/
73 CRC logic changed. mohor 7572d 02h /dbg_interface/trunk/bench/verilog/
63 Three more chains added for cpu debug access. simons 7628d 05h /dbg_interface/trunk/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8106d 04h /dbg_interface/trunk/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8162d 04h /dbg_interface/trunk/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8166d 03h /dbg_interface/trunk/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8306d 07h /dbg_interface/trunk/bench/verilog/
15 bs_chain_o added. mohor 8308d 08h /dbg_interface/trunk/bench/verilog/
13 Signal names changed to lowercase. mohor 8309d 09h /dbg_interface/trunk/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8310d 09h /dbg_interface/trunk/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8331d 05h /dbg_interface/trunk/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8335d 09h /dbg_interface/trunk/bench/verilog/
6 Minor changes for simulation. mohor 8336d 07h /dbg_interface/trunk/bench/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8337d 04h /dbg_interface/trunk/bench/verilog/
2 Initial official release. mohor 8342d 05h /dbg_interface/trunk/bench/verilog/

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