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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 113

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Rev Log message Author Age Path
113 IDCODE test improved. mohor 7536d 22h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7537d 16h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7537d 16h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7537d 17h /dbg_interface/trunk/bench/verilog/
102 New version. mohor 7539d 12h /dbg_interface/trunk/bench/verilog/
101 Almost finished. mohor 7539d 13h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7540d 15h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7541d 19h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7542d 07h /dbg_interface/trunk/bench/verilog/
93 tmp version. mohor 7543d 18h /dbg_interface/trunk/bench/verilog/
92 temp version. mohor 7546d 22h /dbg_interface/trunk/bench/verilog/
91 tmp version. mohor 7547d 17h /dbg_interface/trunk/bench/verilog/
90 tmp version. mohor 7548d 12h /dbg_interface/trunk/bench/verilog/
89 temp4 version. mohor 7549d 18h /dbg_interface/trunk/bench/verilog/
88 temp3 version. mohor 7550d 12h /dbg_interface/trunk/bench/verilog/
87 tmp2 version. mohor 7551d 17h /dbg_interface/trunk/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7564d 15h /dbg_interface/trunk/bench/verilog/
75 Simulation files. mohor 7625d 13h /dbg_interface/trunk/bench/verilog/
73 CRC logic changed. mohor 7625d 13h /dbg_interface/trunk/bench/verilog/
63 Three more chains added for cpu debug access. simons 7681d 16h /dbg_interface/trunk/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8159d 15h /dbg_interface/trunk/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8215d 15h /dbg_interface/trunk/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8219d 14h /dbg_interface/trunk/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8359d 18h /dbg_interface/trunk/bench/verilog/
15 bs_chain_o added. mohor 8361d 19h /dbg_interface/trunk/bench/verilog/
13 Signal names changed to lowercase. mohor 8362d 19h /dbg_interface/trunk/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8363d 20h /dbg_interface/trunk/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8384d 16h /dbg_interface/trunk/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8388d 19h /dbg_interface/trunk/bench/verilog/
6 Minor changes for simulation. mohor 8389d 18h /dbg_interface/trunk/bench/verilog/

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