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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 114

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Rev Log message Author Age Path
114 CRC generation iand verification in bench changed. mohor 7483d 12h /dbg_interface/trunk/bench/verilog/
113 IDCODE test improved. mohor 7483d 13h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7484d 07h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7484d 07h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7484d 08h /dbg_interface/trunk/bench/verilog/
102 New version. mohor 7486d 03h /dbg_interface/trunk/bench/verilog/
101 Almost finished. mohor 7486d 04h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7487d 06h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7488d 10h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7488d 22h /dbg_interface/trunk/bench/verilog/
93 tmp version. mohor 7490d 09h /dbg_interface/trunk/bench/verilog/
92 temp version. mohor 7493d 13h /dbg_interface/trunk/bench/verilog/
91 tmp version. mohor 7494d 08h /dbg_interface/trunk/bench/verilog/
90 tmp version. mohor 7495d 03h /dbg_interface/trunk/bench/verilog/
89 temp4 version. mohor 7496d 09h /dbg_interface/trunk/bench/verilog/
88 temp3 version. mohor 7497d 03h /dbg_interface/trunk/bench/verilog/
87 tmp2 version. mohor 7498d 08h /dbg_interface/trunk/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7511d 06h /dbg_interface/trunk/bench/verilog/
75 Simulation files. mohor 7572d 04h /dbg_interface/trunk/bench/verilog/
73 CRC logic changed. mohor 7572d 04h /dbg_interface/trunk/bench/verilog/
63 Three more chains added for cpu debug access. simons 7628d 07h /dbg_interface/trunk/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8106d 06h /dbg_interface/trunk/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8162d 06h /dbg_interface/trunk/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8166d 05h /dbg_interface/trunk/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8306d 09h /dbg_interface/trunk/bench/verilog/
15 bs_chain_o added. mohor 8308d 10h /dbg_interface/trunk/bench/verilog/
13 Signal names changed to lowercase. mohor 8309d 11h /dbg_interface/trunk/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8310d 11h /dbg_interface/trunk/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8331d 07h /dbg_interface/trunk/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8335d 11h /dbg_interface/trunk/bench/verilog/

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