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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 116

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Rev Log message Author Age Path
116 Data latching changed when testing WB. mohor 7512d 22h /dbg_interface/trunk/bench/verilog/
115 More debug data added. mohor 7513d 02h /dbg_interface/trunk/bench/verilog/
114 CRC generation iand verification in bench changed. mohor 7513d 03h /dbg_interface/trunk/bench/verilog/
113 IDCODE test improved. mohor 7513d 04h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7513d 23h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7513d 23h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7514d 00h /dbg_interface/trunk/bench/verilog/
102 New version. mohor 7515d 18h /dbg_interface/trunk/bench/verilog/
101 Almost finished. mohor 7515d 19h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7516d 21h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7518d 01h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7518d 13h /dbg_interface/trunk/bench/verilog/
93 tmp version. mohor 7520d 01h /dbg_interface/trunk/bench/verilog/
92 temp version. mohor 7523d 04h /dbg_interface/trunk/bench/verilog/
91 tmp version. mohor 7523d 23h /dbg_interface/trunk/bench/verilog/
90 tmp version. mohor 7524d 18h /dbg_interface/trunk/bench/verilog/
89 temp4 version. mohor 7526d 00h /dbg_interface/trunk/bench/verilog/
88 temp3 version. mohor 7526d 19h /dbg_interface/trunk/bench/verilog/
87 tmp2 version. mohor 7528d 00h /dbg_interface/trunk/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7540d 22h /dbg_interface/trunk/bench/verilog/
75 Simulation files. mohor 7601d 20h /dbg_interface/trunk/bench/verilog/
73 CRC logic changed. mohor 7601d 20h /dbg_interface/trunk/bench/verilog/
63 Three more chains added for cpu debug access. simons 7657d 22h /dbg_interface/trunk/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8135d 21h /dbg_interface/trunk/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8191d 22h /dbg_interface/trunk/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8195d 21h /dbg_interface/trunk/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8336d 01h /dbg_interface/trunk/bench/verilog/
15 bs_chain_o added. mohor 8338d 02h /dbg_interface/trunk/bench/verilog/
13 Signal names changed to lowercase. mohor 8339d 02h /dbg_interface/trunk/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8340d 02h /dbg_interface/trunk/bench/verilog/

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