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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 138

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Rev Log message Author Age Path
138 Temp version before changing dbg interface. igorm 7450d 22h /dbg_interface/trunk/bench/verilog/
135 'hz changed to 1'hz because Icarus complains. igorm 7457d 22h /dbg_interface/trunk/bench/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7503d 04h /dbg_interface/trunk/bench/verilog/
124 Display for VATS added. mohor 7508d 00h /dbg_interface/trunk/bench/verilog/
121 Port signals are all set to zero after reset. mohor 7511d 00h /dbg_interface/trunk/bench/verilog/
120 test stall_test added. mohor 7511d 03h /dbg_interface/trunk/bench/verilog/
117 Define name changed. mohor 7513d 00h /dbg_interface/trunk/bench/verilog/
116 Data latching changed when testing WB. mohor 7513d 00h /dbg_interface/trunk/bench/verilog/
115 More debug data added. mohor 7513d 04h /dbg_interface/trunk/bench/verilog/
114 CRC generation iand verification in bench changed. mohor 7513d 05h /dbg_interface/trunk/bench/verilog/
113 IDCODE test improved. mohor 7513d 06h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7514d 01h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7514d 01h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7514d 02h /dbg_interface/trunk/bench/verilog/
102 New version. mohor 7515d 20h /dbg_interface/trunk/bench/verilog/
101 Almost finished. mohor 7515d 21h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7516d 23h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7518d 03h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7518d 15h /dbg_interface/trunk/bench/verilog/
93 tmp version. mohor 7520d 03h /dbg_interface/trunk/bench/verilog/
92 temp version. mohor 7523d 06h /dbg_interface/trunk/bench/verilog/
91 tmp version. mohor 7524d 01h /dbg_interface/trunk/bench/verilog/
90 tmp version. mohor 7524d 20h /dbg_interface/trunk/bench/verilog/
89 temp4 version. mohor 7526d 02h /dbg_interface/trunk/bench/verilog/
88 temp3 version. mohor 7526d 21h /dbg_interface/trunk/bench/verilog/
87 tmp2 version. mohor 7528d 02h /dbg_interface/trunk/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7541d 00h /dbg_interface/trunk/bench/verilog/
75 Simulation files. mohor 7601d 22h /dbg_interface/trunk/bench/verilog/
73 CRC logic changed. mohor 7601d 22h /dbg_interface/trunk/bench/verilog/
63 Three more chains added for cpu debug access. simons 7658d 00h /dbg_interface/trunk/bench/verilog/

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