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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5585d 00h /dbg_interface/trunk/rtl/verilog/
152 CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
check-in.		 igorm 7382d 06h /dbg_interface/trunk/rtl/verilog/
150 Zero is shifted out when CTRL_READ command is active. igorm 7383d 01h /dbg_interface/trunk/rtl/verilog/
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7385d 06h /dbg_interface/trunk/rtl/verilog/
146 Changes for the FormalPRO. igorm 7389d 03h /dbg_interface/trunk/rtl/verilog/
144 Port names and defines for the supported CPUs changed. igorm 7389d 08h /dbg_interface/trunk/rtl/verilog/
143 Signals for easier debugging removed. igorm 7389d 10h /dbg_interface/trunk/rtl/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7390d 06h /dbg_interface/trunk/rtl/verilog/
139 New release of the debug interface (3rd. release). igorm 7393d 00h /dbg_interface/trunk/rtl/verilog/
138 Temp version before changing dbg interface. igorm 7399d 04h /dbg_interface/trunk/rtl/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7451d 10h /dbg_interface/trunk/rtl/verilog/
123 All flipflops are reset. mohor 7456d 06h /dbg_interface/trunk/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7459d 06h /dbg_interface/trunk/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7459d 10h /dbg_interface/trunk/rtl/verilog/
117 Define name changed. mohor 7461d 06h /dbg_interface/trunk/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7462d 13h /dbg_interface/trunk/rtl/verilog/
106 Sensitivity list updated. simons 7463d 11h /dbg_interface/trunk/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7464d 02h /dbg_interface/trunk/rtl/verilog/
102 New version. mohor 7464d 02h /dbg_interface/trunk/rtl/verilog/
101 Almost finished. mohor 7464d 03h /dbg_interface/trunk/rtl/verilog/
100 *** empty log message *** mohor 7465d 05h /dbg_interface/trunk/rtl/verilog/
99 cpu registers added. mohor 7465d 05h /dbg_interface/trunk/rtl/verilog/
97 Working. mohor 7466d 08h /dbg_interface/trunk/rtl/verilog/
95 Temp version. mohor 7466d 21h /dbg_interface/trunk/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7467d 08h /dbg_interface/trunk/rtl/verilog/
93 tmp version. mohor 7468d 09h /dbg_interface/trunk/rtl/verilog/
92 temp version. mohor 7471d 12h /dbg_interface/trunk/rtl/verilog/
91 tmp version. mohor 7472d 08h /dbg_interface/trunk/rtl/verilog/
90 tmp version. mohor 7473d 02h /dbg_interface/trunk/rtl/verilog/
89 temp4 version. mohor 7474d 08h /dbg_interface/trunk/rtl/verilog/

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