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URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] - Rev 326

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Rev Log message Author Age Path
326 RAM simulation access times set to realistic values hellwig 3205d 13h /eco32/
325 memory speed measurement for new controller added hellwig 3214d 05h /eco32/
324 README updated hellwig 3214d 05h /eco32/
323 memspeed renamed to memspeed-1 hellwig 3214d 05h /eco32/
322 README updated, Makefile added hellwig 3214d 17h /eco32/
321 README updated hellwig 3214d 18h /eco32/
320 README updated hellwig 3215d 14h /eco32/
319 memory controller 2, FPGA realization hellwig 3215d 19h /eco32/
318 memory controller 1, FPGA realization hellwig 3215d 19h /eco32/
317 README updated hellwig 3216d 10h /eco32/
316 README added hellwig 3216d 13h /eco32/
315 README added hellwig 3216d 13h /eco32/
314 memory controller simulation 2 hellwig 3216d 15h /eco32/
313 memory controller simulation 1 hellwig 3216d 16h /eco32/
312 memory controller simulation 0 hellwig 3216d 17h /eco32/
311 README updated hellwig 3216d 19h /eco32/
310 verilated mc implementation with and without trace hellwig 3217d 15h /eco32/
309 multicycle simulation of ECO32, using Verilator hellwig 3218d 16h /eco32/
308 multicycle design, suitable for being verilated hellwig 3218d 20h /eco32/
307 several tests got duration.dat files hellwig 3219d 09h /eco32/
306 tool to show display output added hellwig 3219d 17h /eco32/
305 tool to show serial output added hellwig 3219d 17h /eco32/
304 Makefile updated hellwig 3222d 04h /eco32/
303 multicycle simulation control files added hellwig 3222d 04h /eco32/
302 tests updated hellwig 3222d 09h /eco32/
301 multicycle simulation source files added hellwig 3222d 17h /eco32/
300 memdelay experiment code looking better now hellwig 3222d 17h /eco32/
299 s3e-500 dac simulation corrected hellwig 3222d 18h /eco32/
298 xsa-xst-3 dac simulation corrected hellwig 3222d 18h /eco32/
297 memdelay experiment added hellwig 3222d 19h /eco32/

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