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Subversion Repositories eco32

[/] [eco32/] - Rev 332

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Rev Log message Author Age Path
332 update COPYING hellwig 2818d 07h /eco32/
331 machine monitor: init kbd and dsp only if explicitly requested hellwig 2818d 20h /eco32/
330 sim/getline/testgl.c: return type of main() changed to int hellwig 2818d 21h /eco32/
329 lcc/lburg/gram.y: prototype for yylex() added hellwig 2818d 21h /eco32/
328 lcc/etc/lcc.c: return type of main() changed to int hellwig 2818d 21h /eco32/
327 flag -m32 in compilation of vcdchk deleted hellwig 3086d 07h /eco32/
326 RAM simulation access times set to realistic values hellwig 3197d 01h /eco32/
325 memory speed measurement for new controller added hellwig 3205d 17h /eco32/
324 README updated hellwig 3205d 17h /eco32/
323 memspeed renamed to memspeed-1 hellwig 3205d 18h /eco32/
322 README updated, Makefile added hellwig 3206d 05h /eco32/
321 README updated hellwig 3206d 06h /eco32/
320 README updated hellwig 3207d 02h /eco32/
319 memory controller 2, FPGA realization hellwig 3207d 07h /eco32/
318 memory controller 1, FPGA realization hellwig 3207d 07h /eco32/
317 README updated hellwig 3207d 22h /eco32/
316 README added hellwig 3208d 01h /eco32/
315 README added hellwig 3208d 01h /eco32/
314 memory controller simulation 2 hellwig 3208d 03h /eco32/
313 memory controller simulation 1 hellwig 3208d 04h /eco32/
312 memory controller simulation 0 hellwig 3208d 06h /eco32/
311 README updated hellwig 3208d 07h /eco32/
310 verilated mc implementation with and without trace hellwig 3209d 03h /eco32/
309 multicycle simulation of ECO32, using Verilator hellwig 3210d 04h /eco32/
308 multicycle design, suitable for being verilated hellwig 3210d 08h /eco32/
307 several tests got duration.dat files hellwig 3210d 21h /eco32/
306 tool to show display output added hellwig 3211d 05h /eco32/
305 tool to show serial output added hellwig 3211d 05h /eco32/
304 Makefile updated hellwig 3213d 16h /eco32/
303 multicycle simulation control files added hellwig 3213d 16h /eco32/

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