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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] - Rev 308

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Rev Log message Author Age Path
291 avoid timing violations in DDR RAM circuit, new .bit files generated hellwig 3288d 08h /eco32/trunk/fpga/mc/src/
290 Wishbone-compatible bus signals hellwig 3290d 08h /eco32/trunk/fpga/mc/src/
288 new directory structure within fpga hellwig 3291d 05h /eco32/trunk/fpga/mc/src/
231 DAC controller added to ECO32 for XESS board hellwig 3610d 01h /eco32/trunk/fpga/src/
229 organizing hardware hellwig 3610d 15h /eco32/trunk/fpga/src/
226 organizing hardware hellwig 3614d 11h /eco32/trunk/fpga/src/
221 organizing hardware hellwig 3614d 12h /eco32/trunk/fpga/src/
220 organizing hardware hellwig 3614d 12h /eco32/trunk/fpga/src/
219 organizing hardware hellwig 3614d 15h /eco32/trunk/fpga/src/
218 organizing hardware hellwig 3615d 10h /eco32/trunk/fpga/src/
216 organizing hardware hellwig 3615d 15h /eco32/trunk/fpga/src/
215 organizing hardware hellwig 3615d 16h /eco32/trunk/fpga/src/
204 changed TLB behavior on tbs instructions hellwig 3627d 10h /eco32/trunk/fpga/src/
197 IDE interface byte-order problem solved hellwig 3636d 12h /eco32/trunk/fpga/src/
192 board I/O for XSA board hellwig 3639d 08h /eco32/trunk/fpga/src/
191 board I/O for XSA board hellwig 3639d 10h /eco32/trunk/fpga/src/
190 board-specific I/O module added hellwig 3639d 15h /eco32/trunk/fpga/src/
181 hardware got BadAccess register; synthesizer result eco32.bit now included hellwig 3645d 07h /eco32/trunk/fpga/src/
129 hardware: clock/reset update hellwig 3799d 15h /eco32/trunk/fpga/src/
128 hardware: clock/reset update hellwig 3799d 15h /eco32/trunk/fpga/src/
127 hardware: clock/reset update hellwig 3800d 02h /eco32/trunk/fpga/src/
126 hardware: ram pin ordering hellwig 3800d 14h /eco32/trunk/fpga/src/
125 hardware: cpu external pin ordering hellwig 3800d 14h /eco32/trunk/fpga/src/
124 hardware: busctrl source formatted hellwig 3800d 23h /eco32/trunk/fpga/src/
123 hardware: dsp now equivalent to port-15 hellwig 3801d 02h /eco32/trunk/fpga/src/
122 hardware: in sdramcntl.v signal added to sensitivity list hellwig 3801d 08h /eco32/trunk/fpga/src/
121 hardware: dsk source formatted hellwig 3801d 12h /eco32/trunk/fpga/src/
120 hardware: in cpu/sregs change signal names di->din, do->dout hellwig 3801d 14h /eco32/trunk/fpga/src/
119 hardware: ram now equivalent to port-15 hellwig 3802d 00h /eco32/trunk/fpga/src/
118 hardware: rom now equivalent to port-15 hellwig 3802d 13h /eco32/trunk/fpga/src/

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