OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] - Rev 226

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7902d 01h /ethmac/branches/unneback/
225 Some minor changes. tadejm 7902d 01h /ethmac/branches/unneback/
224 Signals for a wave window in Modelsim. tadejm 7902d 02h /ethmac/branches/unneback/
223 Some code changed due to bug fixes. tadejm 7902d 02h /ethmac/branches/unneback/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7906d 00h /ethmac/branches/unneback/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7909d 01h /ethmac/branches/unneback/
218 Typo error fixed. (When using Bist) mohor 7909d 03h /ethmac/branches/unneback/
217 Bist supported. mohor 7909d 03h /ethmac/branches/unneback/
216 Bist signals added. mohor 7909d 03h /ethmac/branches/unneback/
215 Bist supported. mohor 7909d 04h /ethmac/branches/unneback/
214 Signals for WISHBONE B3 compliant interface added. mohor 7910d 00h /ethmac/branches/unneback/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7910d 00h /ethmac/branches/unneback/
212 Minor $display change. mohor 7910d 00h /ethmac/branches/unneback/
211 Bist added. mohor 7910d 00h /ethmac/branches/unneback/
210 BIST added. mohor 7910d 00h /ethmac/branches/unneback/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7911d 03h /ethmac/branches/unneback/
208 Virtual Silicon RAMs moved to lib directory tadej 7926d 21h /ethmac/branches/unneback/
207 Virtual Silicon RAM support fixed tadej 7926d 21h /ethmac/branches/unneback/
206 Virtual Silicon RAM added to the simulation. mohor 7926d 21h /ethmac/branches/unneback/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7926d 22h /ethmac/branches/unneback/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7926d 22h /ethmac/branches/unneback/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7926d 22h /ethmac/branches/unneback/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7929d 23h /ethmac/branches/unneback/
201 Core size added to the document. mohor 7930d 00h /ethmac/branches/unneback/
200 File with lower case checked in instead. mohor 7930d 00h /ethmac/branches/unneback/
199 Datasheet name changed to lower case name. mohor 7930d 00h /ethmac/branches/unneback/
198 Removed file. File with name in lower case will be added instead. mohor 7930d 00h /ethmac/branches/unneback/
197 Ethernet Data Sheet. mohor 7930d 00h /ethmac/branches/unneback/
196 Ethernet product brief. mohor 7930d 01h /ethmac/branches/unneback/
195 Product brief removed because it is the same as Datasheet. mohor 7930d 01h /ethmac/branches/unneback/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.