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Rev Log message Author Age Path
49 HASH0 and HASH1 register read/write added. mohor 8244d 05h /ethmac/branches/unneback/
48 RxOverRun added to statuses. mohor 8244d 08h /ethmac/branches/unneback/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8244d 08h /ethmac/branches/unneback/
46 HASH0 and HASH1 registers added. mohor 8244d 08h /ethmac/branches/unneback/
45 Ethernet Datasheet added. mohor 8244d 14h /ethmac/branches/unneback/
44 Ethernet Datasheet added to cvs. mohor 8244d 14h /ethmac/branches/unneback/
43 Tx status is written back to the BD. mohor 8245d 16h /ethmac/branches/unneback/
42 Rx status is written back to the BD. mohor 8248d 09h /ethmac/branches/unneback/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8250d 11h /ethmac/branches/unneback/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8251d 08h /ethmac/branches/unneback/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8255d 12h /ethmac/branches/unneback/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8264d 14h /ethmac/branches/unneback/
37 Link in the header changed. mohor 8264d 14h /ethmac/branches/unneback/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8310d 12h /ethmac/branches/unneback/
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8313d 10h /ethmac/branches/unneback/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8313d 10h /ethmac/branches/unneback/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8313d 14h /ethmac/branches/unneback/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8313d 15h /ethmac/branches/unneback/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8313d 15h /ethmac/branches/unneback/
30 BD section updated. mohor 8315d 12h /ethmac/branches/unneback/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8335d 11h /ethmac/branches/unneback/
28 New release. Name changed to lower case. mohor 8338d 02h /ethmac/branches/unneback/
27 File names changed to lower case. mohor 8338d 02h /ethmac/branches/unneback/
26 First release of product brief. mohor 8338d 02h /ethmac/branches/unneback/
25 First release of product brief. mohor 8338d 02h /ethmac/branches/unneback/
24 Log file added. mohor 8360d 13h /ethmac/branches/unneback/
23 Number of addresses (wb_adr_i) minimized. mohor 8360d 14h /ethmac/branches/unneback/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8360d 16h /ethmac/branches/unneback/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8361d 13h /ethmac/branches/unneback/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8385d 10h /ethmac/branches/unneback/

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