OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] - Rev 304

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7507d 01h /ethmac/branches/unneback/rtl/
302 mbist signals updated according to newest convention markom 7533d 11h /ethmac/branches/unneback/rtl/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7544d 03h /ethmac/branches/unneback/rtl/
297 Artisan ram instance added. simons 7597d 02h /ethmac/branches/unneback/rtl/
288 This file was not part of the RTL before, but it should be here. simons 7633d 04h /ethmac/branches/unneback/rtl/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7659d 07h /ethmac/branches/unneback/rtl/
285 Binary operator used instead of unary (xnor). mohor 7659d 08h /ethmac/branches/unneback/rtl/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7687d 09h /ethmac/branches/unneback/rtl/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7715d 03h /ethmac/branches/unneback/rtl/
280 Reset has priority in some flipflops. mohor 7793d 04h /ethmac/branches/unneback/rtl/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7793d 06h /ethmac/branches/unneback/rtl/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7793d 06h /ethmac/branches/unneback/rtl/
276 Defer indication changed. tadejm 7793d 06h /ethmac/branches/unneback/rtl/
275 Fix MTxErr or prevent sending too big frames. mohor 7800d 10h /ethmac/branches/unneback/rtl/
272 When control packets were received, they were ignored in some cases. tadejm 7801d 05h /ethmac/branches/unneback/rtl/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7802d 07h /ethmac/branches/unneback/rtl/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7803d 07h /ethmac/branches/unneback/rtl/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7862d 06h /ethmac/branches/unneback/rtl/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7862d 17h /ethmac/branches/unneback/rtl/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7863d 19h /ethmac/branches/unneback/rtl/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7863d 19h /ethmac/branches/unneback/rtl/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7863d 19h /ethmac/branches/unneback/rtl/
255 TPauseRq synchronized to tx_clk. mohor 7863d 19h /ethmac/branches/unneback/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7865d 01h /ethmac/branches/unneback/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7865d 02h /ethmac/branches/unneback/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7865d 02h /ethmac/branches/unneback/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7866d 02h /ethmac/branches/unneback/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7869d 05h /ethmac/branches/unneback/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7870d 01h /ethmac/branches/unneback/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7870d 21h /ethmac/branches/unneback/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.