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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 346

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Rev Log message Author Age Path
346 Updated project location olof 4707d 17h /ethmac/branches/unneback/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4717d 17h /ethmac/branches/unneback/rtl/verilog/
338 root 5511d 19h /ethmac/branches/unneback/rtl/verilog/
335 New directory structure. root 5569d 01h /ethmac/branches/unneback/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7017d 14h /ethmac/branches/unneback/rtl/verilog/
332 Case statement improved for synthesys. igorm 7030d 20h /ethmac/branches/unneback/rtl/verilog/
330 Warning fixes. igorm 7045d 22h /ethmac/branches/unneback/rtl/verilog/
329 Defer indication fixed. igorm 7045d 23h /ethmac/branches/unneback/rtl/verilog/
328 Delayed CRC fixed. igorm 7045d 23h /ethmac/branches/unneback/rtl/verilog/
327 Defer indication fixed. igorm 7045d 23h /ethmac/branches/unneback/rtl/verilog/
326 Delayed CRC fixed. igorm 7046d 00h /ethmac/branches/unneback/rtl/verilog/
325 Defer indication fixed. igorm 7046d 00h /ethmac/branches/unneback/rtl/verilog/
323 Accidently deleted line put back. igorm 7343d 00h /ethmac/branches/unneback/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7346d 19h /ethmac/branches/unneback/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7346d 23h /ethmac/branches/unneback/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7387d 01h /ethmac/branches/unneback/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7489d 22h /ethmac/branches/unneback/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 7490d 20h /ethmac/branches/unneback/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7512d 16h /ethmac/branches/unneback/rtl/verilog/
302 mbist signals updated according to newest convention markom 7539d 03h /ethmac/branches/unneback/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7549d 19h /ethmac/branches/unneback/rtl/verilog/
297 Artisan ram instance added. simons 7602d 18h /ethmac/branches/unneback/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 7638d 20h /ethmac/branches/unneback/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7664d 23h /ethmac/branches/unneback/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 7664d 23h /ethmac/branches/unneback/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7693d 00h /ethmac/branches/unneback/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7720d 18h /ethmac/branches/unneback/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7798d 20h /ethmac/branches/unneback/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7798d 21h /ethmac/branches/unneback/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7798d 21h /ethmac/branches/unneback/rtl/verilog/

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