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[/] [ethmac/] [tags/] [asyst_2/] - Rev 37

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Rev	Log message	Author	Age	Path
37	Link in the header changed.	mohor	8188d 01h	/ethmac/tags/asyst_2/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8233d 23h	/ethmac/tags/asyst_2/
35	RX_BD_NUM changed to TX_BD_NUM. Few typos corrected.	mohor	8236d 21h	/ethmac/tags/asyst_2/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8236d 21h	/ethmac/tags/asyst_2/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8237d 01h	/ethmac/tags/asyst_2/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8237d 02h	/ethmac/tags/asyst_2/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8237d 02h	/ethmac/tags/asyst_2/
30	BD section updated.	mohor	8238d 23h	/ethmac/tags/asyst_2/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8258d 22h	/ethmac/tags/asyst_2/
28	New release. Name changed to lower case.	mohor	8261d 13h	/ethmac/tags/asyst_2/
27	File names changed to lower case.	mohor	8261d 13h	/ethmac/tags/asyst_2/
26	First release of product brief.	mohor	8261d 13h	/ethmac/tags/asyst_2/
25	First release of product brief.	mohor	8261d 13h	/ethmac/tags/asyst_2/
24	Log file added.	mohor	8284d 00h	/ethmac/tags/asyst_2/
23	Number of addresses (wb_adr_i) minimized.	mohor	8284d 01h	/ethmac/tags/asyst_2/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8284d 03h	/ethmac/tags/asyst_2/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8285d 00h	/ethmac/tags/asyst_2/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8308d 21h	/ethmac/tags/asyst_2/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8308d 21h	/ethmac/tags/asyst_2/
18	Few little NCSIM warnings fixed.	mohor	8321d 22h	/ethmac/tags/asyst_2/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8348d 22h	/ethmac/tags/asyst_2/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8356d 03h	/ethmac/tags/asyst_2/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8357d 21h	/ethmac/tags/asyst_2/
14	Unconnected signals are now connected.	mohor	8362d 03h	/ethmac/tags/asyst_2/
13	New directory structure. Files upodated and put together.	mohor	8364d 11h	/ethmac/tags/asyst_2/
12	Directory structure changed. Files checked and joind together.	mohor	8364d 14h	/ethmac/tags/asyst_2/
11	Directory structure changed. Files checked and joind together.	mohor	8364d 14h	/ethmac/tags/asyst_2/
10	Directory structure changed. Files checked and joind together.	mohor	8364d 15h	/ethmac/tags/asyst_2/
9	Documentation updated to be synchronized to the verilog files.	mohor	8391d 23h	/ethmac/tags/asyst_2/
8	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8419d 04h	/ethmac/tags/asyst_2/

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[/] [ethmac/] [tags/] [asyst_2/] - Rev 37

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