OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 Reset values are passed to registers through parameters mohor 8152d 17h /ethmac/tags/rel_1/rtl/verilog/
73 Number of interrupts changed mohor 8152d 17h /ethmac/tags/rel_1/rtl/verilog/
72 Retry is not activated when a Tx Underrun occured mohor 8156d 20h /ethmac/tags/rel_1/rtl/verilog/
70 Small fixes. mohor 8160d 23h /ethmac/tags/rel_1/rtl/verilog/
69 Define missmatch fixed. mohor 8161d 20h /ethmac/tags/rel_1/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 8162d 19h /ethmac/tags/rel_1/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8162d 20h /ethmac/tags/rel_1/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 8163d 02h /ethmac/tags/rel_1/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8163d 16h /ethmac/tags/rel_1/rtl/verilog/
63 RxAbort is connected differently. mohor 8163d 19h /ethmac/tags/rel_1/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 8163d 19h /ethmac/tags/rel_1/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 8163d 21h /ethmac/tags/rel_1/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8163d 21h /ethmac/tags/rel_1/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8163d 22h /ethmac/tags/rel_1/rtl/verilog/
58 File format changed. mohor 8163d 22h /ethmac/tags/rel_1/rtl/verilog/
57 Format of the file changed a bit. mohor 8163d 22h /ethmac/tags/rel_1/rtl/verilog/
56 File format fixed a bit. mohor 8163d 22h /ethmac/tags/rel_1/rtl/verilog/
55 Changed that were lost with last update put back to the file. mohor 8163d 22h /ethmac/tags/rel_1/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 8164d 12h /ethmac/tags/rel_1/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 8164d 12h /ethmac/tags/rel_1/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8164d 13h /ethmac/tags/rel_1/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8164d 14h /ethmac/tags/rel_1/rtl/verilog/
48 RxOverRun added to statuses. mohor 8166d 16h /ethmac/tags/rel_1/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8166d 16h /ethmac/tags/rel_1/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 8166d 16h /ethmac/tags/rel_1/rtl/verilog/
43 Tx status is written back to the BD. mohor 8168d 00h /ethmac/tags/rel_1/rtl/verilog/
42 Rx status is written back to the BD. mohor 8170d 17h /ethmac/tags/rel_1/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8172d 19h /ethmac/tags/rel_1/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8173d 16h /ethmac/tags/rel_1/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8177d 20h /ethmac/tags/rel_1/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.