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[/] [ethmac/] [tags/] [rel_10/] - Rev 146

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Rev	Log message	Author	Age	Path
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	8032d 00h	/ethmac/tags/rel_10/
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	8032d 00h	/ethmac/tags/rel_10/
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	8048d 03h	/ethmac/tags/rel_10/
141	Syntax error fixed.	mohor	8050d 20h	/ethmac/tags/rel_10/
140	Syntax error fixed.	mohor	8050d 20h	/ethmac/tags/rel_10/
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	8050d 20h	/ethmac/tags/rel_10/
138	Synchronous reset added.	mohor	8050d 20h	/ethmac/tags/rel_10/
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	8050d 20h	/ethmac/tags/rel_10/
136	Parameter ResetValue changed to capital letters.	mohor	8051d 06h	/ethmac/tags/rel_10/
135	New revision. External DMA removed, TX_BD_NUM changed.	mohor	8052d 22h	/ethmac/tags/rel_10/
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	8052d 23h	/ethmac/tags/rel_10/
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	8053d 00h	/ethmac/tags/rel_10/
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	8053d 00h	/ethmac/tags/rel_10/
131	LinkFail signal was not latching appropriate bit.	mohor	8053d 00h	/ethmac/tags/rel_10/
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	8053d 01h	/ethmac/tags/rel_10/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	8053d 01h	/ethmac/tags/rel_10/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	8073d 00h	/ethmac/tags/rel_10/
126	InvalidSymbol generation changed.	mohor	8073d 00h	/ethmac/tags/rel_10/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	8073d 00h	/ethmac/tags/rel_10/
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	8073d 01h	/ethmac/tags/rel_10/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	8075d 02h	/ethmac/tags/rel_10/
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	8075d 02h	/ethmac/tags/rel_10/
120	Unused files removed.	mohor	8075d 03h	/ethmac/tags/rel_10/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	8075d 03h	/ethmac/tags/rel_10/
118	ShiftEnded synchronization changed.	mohor	8078d 18h	/ethmac/tags/rel_10/
117	Clock mrx_clk set to 2.5 MHz.	mohor	8079d 05h	/ethmac/tags/rel_10/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	8079d 05h	/ethmac/tags/rel_10/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	8080d 02h	/ethmac/tags/rel_10/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	8081d 00h	/ethmac/tags/rel_10/
113	RxPointer bug fixed.	mohor	8087d 16h	/ethmac/tags/rel_10/

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[/] [ethmac/] [tags/] [rel_10/] - Rev 146

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