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Rev Log message Author Age Path
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8211d 22h /ethmac/tags/rel_12/
46 HASH0 and HASH1 registers added. mohor 8211d 22h /ethmac/tags/rel_12/
45 Ethernet Datasheet added. mohor 8212d 04h /ethmac/tags/rel_12/
44 Ethernet Datasheet added to cvs. mohor 8212d 04h /ethmac/tags/rel_12/
43 Tx status is written back to the BD. mohor 8213d 05h /ethmac/tags/rel_12/
42 Rx status is written back to the BD. mohor 8215d 22h /ethmac/tags/rel_12/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8218d 01h /ethmac/tags/rel_12/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8218d 22h /ethmac/tags/rel_12/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8223d 02h /ethmac/tags/rel_12/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8232d 04h /ethmac/tags/rel_12/
37 Link in the header changed. mohor 8232d 04h /ethmac/tags/rel_12/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8278d 02h /ethmac/tags/rel_12/
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8281d 00h /ethmac/tags/rel_12/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8281d 00h /ethmac/tags/rel_12/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8281d 04h /ethmac/tags/rel_12/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8281d 04h /ethmac/tags/rel_12/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8281d 05h /ethmac/tags/rel_12/
30 BD section updated. mohor 8283d 02h /ethmac/tags/rel_12/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8303d 00h /ethmac/tags/rel_12/
28 New release. Name changed to lower case. mohor 8305d 16h /ethmac/tags/rel_12/
27 File names changed to lower case. mohor 8305d 16h /ethmac/tags/rel_12/
26 First release of product brief. mohor 8305d 16h /ethmac/tags/rel_12/
25 First release of product brief. mohor 8305d 16h /ethmac/tags/rel_12/
24 Log file added. mohor 8328d 03h /ethmac/tags/rel_12/
23 Number of addresses (wb_adr_i) minimized. mohor 8328d 03h /ethmac/tags/rel_12/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8328d 06h /ethmac/tags/rel_12/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8329d 03h /ethmac/tags/rel_12/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8353d 00h /ethmac/tags/rel_12/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8353d 00h /ethmac/tags/rel_12/
18 Few little NCSIM warnings fixed. mohor 8366d 00h /ethmac/tags/rel_12/

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