OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 125

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7985d 15h /ethmac/tags/rel_12/rtl/verilog/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7987d 16h /ethmac/tags/rel_12/rtl/verilog/
120 Unused files removed. mohor 7987d 17h /ethmac/tags/rel_12/rtl/verilog/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7987d 17h /ethmac/tags/rel_12/rtl/verilog/
118 ShiftEnded synchronization changed. mohor 7991d 08h /ethmac/tags/rel_12/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7992d 17h /ethmac/tags/rel_12/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7993d 14h /ethmac/tags/rel_12/rtl/verilog/
113 RxPointer bug fixed. mohor 8000d 06h /ethmac/tags/rel_12/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8000d 20h /ethmac/tags/rel_12/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8001d 09h /ethmac/tags/rel_12/rtl/verilog/
110 m_wb_cyc_o signal released after every single transfer. mohor 8001d 12h /ethmac/tags/rel_12/rtl/verilog/
109 Comment removed. mohor 8001d 13h /ethmac/tags/rel_12/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8068d 23h /ethmac/tags/rel_12/rtl/verilog/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8078d 00h /ethmac/tags/rel_12/rtl/verilog/
104 FCS should not be included in NibbleMinFl. mohor 8079d 18h /ethmac/tags/rel_12/rtl/verilog/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8079d 19h /ethmac/tags/rel_12/rtl/verilog/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8079d 19h /ethmac/tags/rel_12/rtl/verilog/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8079d 19h /ethmac/tags/rel_12/rtl/verilog/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8079d 19h /ethmac/tags/rel_12/rtl/verilog/
97 Small typo fixed. lampret 8103d 17h /ethmac/tags/rel_12/rtl/verilog/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8107d 17h /ethmac/tags/rel_12/rtl/verilog/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8107d 19h /ethmac/tags/rel_12/rtl/verilog/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8107d 19h /ethmac/tags/rel_12/rtl/verilog/
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8112d 18h /ethmac/tags/rel_12/rtl/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8113d 20h /ethmac/tags/rel_12/rtl/verilog/
91 Comments in Slovene language removed. mohor 8113d 20h /ethmac/tags/rel_12/rtl/verilog/
90 casex changed with case, fifo reset changed. mohor 8113d 20h /ethmac/tags/rel_12/rtl/verilog/
88 rx_fifo was not always cleared ok. Fixed. mohor 8123d 17h /ethmac/tags/rel_12/rtl/verilog/
87 Status was not latched correctly sometimes. Fixed. mohor 8123d 19h /ethmac/tags/rel_12/rtl/verilog/
86 Big Endian problem when sending frames fixed. mohor 8125d 02h /ethmac/tags/rel_12/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.