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[/] [ethmac/] [tags/] [rel_14/] - Rev 132

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Rev	Log message	Author	Age	Path
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7976d 16h	/ethmac/tags/rel_14/
131	LinkFail signal was not latching appropriate bit.	mohor	7976d 16h	/ethmac/tags/rel_14/
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	7976d 16h	/ethmac/tags/rel_14/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7976d 17h	/ethmac/tags/rel_14/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7996d 16h	/ethmac/tags/rel_14/
126	InvalidSymbol generation changed.	mohor	7996d 16h	/ethmac/tags/rel_14/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7996d 16h	/ethmac/tags/rel_14/
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	7996d 17h	/ethmac/tags/rel_14/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7998d 18h	/ethmac/tags/rel_14/
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7998d 18h	/ethmac/tags/rel_14/
120	Unused files removed.	mohor	7998d 19h	/ethmac/tags/rel_14/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7998d 19h	/ethmac/tags/rel_14/
118	ShiftEnded synchronization changed.	mohor	8002d 10h	/ethmac/tags/rel_14/
117	Clock mrx_clk set to 2.5 MHz.	mohor	8002d 20h	/ethmac/tags/rel_14/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	8002d 20h	/ethmac/tags/rel_14/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	8003d 18h	/ethmac/tags/rel_14/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	8004d 16h	/ethmac/tags/rel_14/
113	RxPointer bug fixed.	mohor	8011d 08h	/ethmac/tags/rel_14/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	8011d 21h	/ethmac/tags/rel_14/
111	Master state machine had a bug when switching from master write to master read.	mohor	8012d 11h	/ethmac/tags/rel_14/
110	m_wb_cyc_o signal released after every single transfer.	mohor	8012d 14h	/ethmac/tags/rel_14/
109	Comment removed.	mohor	8012d 14h	/ethmac/tags/rel_14/
108	Testbench supports unaligned accesses.	mohor	8080d 00h	/ethmac/tags/rel_14/
107	TX_BUF_BASE changed.	mohor	8080d 00h	/ethmac/tags/rel_14/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8080d 00h	/ethmac/tags/rel_14/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8089d 02h	/ethmac/tags/rel_14/
104	FCS should not be included in NibbleMinFl.	mohor	8090d 20h	/ethmac/tags/rel_14/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8090d 20h	/ethmac/tags/rel_14/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8090d 20h	/ethmac/tags/rel_14/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8090d 21h	/ethmac/tags/rel_14/

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[/] [ethmac/] [tags/] [rel_14/] - Rev 132

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