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[/] [ethmac/] [tags/] [rel_14/] [bench/] [verilog/] - Rev 254

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Rev Log message Author Age Path
254 Temp version. mohor 7981d 07h /ethmac/tags/rel_14/bench/verilog/
252 Just some updates. tadejm 7981d 10h /ethmac/tags/rel_14/bench/verilog/
243 Late collision is not reported any more. tadejm 7986d 14h /ethmac/tags/rel_14/bench/verilog/
227 Changed BIST scan signals. tadejm 8013d 11h /ethmac/tags/rel_14/bench/verilog/
223 Some code changed due to bug fixes. tadejm 8013d 14h /ethmac/tags/rel_14/bench/verilog/
216 Bist signals added. mohor 8020d 14h /ethmac/tags/rel_14/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 8022d 14h /ethmac/tags/rel_14/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 8041d 13h /ethmac/tags/rel_14/bench/verilog/
192 Some additional reports added tadej 8043d 10h /ethmac/tags/rel_14/bench/verilog/
191 Bug repaired in eth_phy device tadej 8043d 10h /ethmac/tags/rel_14/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 8043d 11h /ethmac/tags/rel_14/bench/verilog/
188 PHY changed. tadej 8044d 08h /ethmac/tags/rel_14/bench/verilog/
182 Full duplex test improved. tadej 8045d 10h /ethmac/tags/rel_14/bench/verilog/
181 MIIM test look better. mohor 8045d 13h /ethmac/tags/rel_14/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 8048d 08h /ethmac/tags/rel_14/bench/verilog/
179 Beautiful tests merget together mohor 8048d 09h /ethmac/tags/rel_14/bench/verilog/
178 Rearanged testcases mohor 8048d 09h /ethmac/tags/rel_14/bench/verilog/
177 Bug in MIIM fixed. mohor 8048d 13h /ethmac/tags/rel_14/bench/verilog/
170 Headers changed. mohor 8048d 15h /ethmac/tags/rel_14/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 8048d 16h /ethmac/tags/rel_14/bench/verilog/
158 Typo fixed. mohor 8053d 11h /ethmac/tags/rel_14/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 8055d 17h /ethmac/tags/rel_14/bench/verilog/
156 Valid testbench. mohor 8055d 17h /ethmac/tags/rel_14/bench/verilog/
155 Minor changes. mohor 8055d 17h /ethmac/tags/rel_14/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8098d 10h /ethmac/tags/rel_14/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8100d 11h /ethmac/tags/rel_14/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 8104d 14h /ethmac/tags/rel_14/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8104d 14h /ethmac/tags/rel_14/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8181d 17h /ethmac/tags/rel_14/bench/verilog/
107 TX_BUF_BASE changed. mohor 8181d 17h /ethmac/tags/rel_14/bench/verilog/

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