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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7874d 09h /ethmac/tags/rel_15/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7876d 14h /ethmac/tags/rel_15/
235 rev 4. mohor 7877d 05h /ethmac/tags/rel_15/
234 Figure list assed to the revision 3. mohor 7877d 13h /ethmac/tags/rel_15/
233 Revision 0.3 released. Some figures added. mohor 7877d 13h /ethmac/tags/rel_15/
232 fpga define added. mohor 7882d 08h /ethmac/tags/rel_15/
231 Description of Core Modules added (figure). mohor 7884d 09h /ethmac/tags/rel_15/
229 case changed to casex. mohor 7888d 06h /ethmac/tags/rel_15/
227 Changed BIST scan signals. tadejm 7888d 10h /ethmac/tags/rel_15/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7888d 11h /ethmac/tags/rel_15/
225 Some minor changes. tadejm 7888d 11h /ethmac/tags/rel_15/
224 Signals for a wave window in Modelsim. tadejm 7888d 13h /ethmac/tags/rel_15/
223 Some code changed due to bug fixes. tadejm 7888d 13h /ethmac/tags/rel_15/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7892d 11h /ethmac/tags/rel_15/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7895d 11h /ethmac/tags/rel_15/
218 Typo error fixed. (When using Bist) mohor 7895d 13h /ethmac/tags/rel_15/
217 Bist supported. mohor 7895d 13h /ethmac/tags/rel_15/
216 Bist signals added. mohor 7895d 13h /ethmac/tags/rel_15/
215 Bist supported. mohor 7895d 14h /ethmac/tags/rel_15/
214 Signals for WISHBONE B3 compliant interface added. mohor 7896d 10h /ethmac/tags/rel_15/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7896d 10h /ethmac/tags/rel_15/
212 Minor $display change. mohor 7896d 10h /ethmac/tags/rel_15/
211 Bist added. mohor 7896d 10h /ethmac/tags/rel_15/
210 BIST added. mohor 7896d 10h /ethmac/tags/rel_15/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7897d 14h /ethmac/tags/rel_15/
208 Virtual Silicon RAMs moved to lib directory tadej 7913d 08h /ethmac/tags/rel_15/
207 Virtual Silicon RAM support fixed tadej 7913d 08h /ethmac/tags/rel_15/
206 Virtual Silicon RAM added to the simulation. mohor 7913d 08h /ethmac/tags/rel_15/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7913d 09h /ethmac/tags/rel_15/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7913d 09h /ethmac/tags/rel_15/

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