OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 92

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8124d 05h /ethmac/tags/rel_17/rtl/verilog/
91 Comments in Slovene language removed. mohor 8124d 05h /ethmac/tags/rel_17/rtl/verilog/
90 casex changed with case, fifo reset changed. mohor 8124d 05h /ethmac/tags/rel_17/rtl/verilog/
88 rx_fifo was not always cleared ok. Fixed. mohor 8134d 02h /ethmac/tags/rel_17/rtl/verilog/
87 Status was not latched correctly sometimes. Fixed. mohor 8134d 04h /ethmac/tags/rel_17/rtl/verilog/
86 Big Endian problem when sending frames fixed. mohor 8135d 11h /ethmac/tags/rel_17/rtl/verilog/
85 Log info was missing. mohor 8140d 21h /ethmac/tags/rel_17/rtl/verilog/
84 LinkFail signal was not latching appropriate bit. mohor 8140d 21h /ethmac/tags/rel_17/rtl/verilog/
83 MAC address recognition was not correct (bytes swaped). mohor 8140d 21h /ethmac/tags/rel_17/rtl/verilog/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8140d 23h /ethmac/tags/rel_17/rtl/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8145d 01h /ethmac/tags/rel_17/rtl/verilog/
79 RetryCntLatched was unused and removed from design mohor 8145d 02h /ethmac/tags/rel_17/rtl/verilog/
78 WB_SEL_I was unused and removed from design mohor 8145d 02h /ethmac/tags/rel_17/rtl/verilog/
77 Interrupts changed mohor 8145d 02h /ethmac/tags/rel_17/rtl/verilog/
76 Interrupts changed in the top file mohor 8145d 02h /ethmac/tags/rel_17/rtl/verilog/
75 r_Bro is used for accepting/denying frames mohor 8145d 02h /ethmac/tags/rel_17/rtl/verilog/
74 Reset values are passed to registers through parameters mohor 8145d 02h /ethmac/tags/rel_17/rtl/verilog/
73 Number of interrupts changed mohor 8145d 02h /ethmac/tags/rel_17/rtl/verilog/
72 Retry is not activated when a Tx Underrun occured mohor 8149d 05h /ethmac/tags/rel_17/rtl/verilog/
70 Small fixes. mohor 8153d 08h /ethmac/tags/rel_17/rtl/verilog/
69 Define missmatch fixed. mohor 8154d 05h /ethmac/tags/rel_17/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 8155d 04h /ethmac/tags/rel_17/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8155d 05h /ethmac/tags/rel_17/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 8155d 11h /ethmac/tags/rel_17/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8156d 01h /ethmac/tags/rel_17/rtl/verilog/
63 RxAbort is connected differently. mohor 8156d 04h /ethmac/tags/rel_17/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 8156d 05h /ethmac/tags/rel_17/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 8156d 06h /ethmac/tags/rel_17/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8156d 06h /ethmac/tags/rel_17/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8156d 07h /ethmac/tags/rel_17/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.