OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_18/] [rtl/] - Rev 64

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8176d 07h /ethmac/tags/rel_18/rtl/
63 RxAbort is connected differently. mohor 8176d 10h /ethmac/tags/rel_18/rtl/
62 RxAbort is an output. No need to have is declared as wire. mohor 8176d 10h /ethmac/tags/rel_18/rtl/
61 RxStartFrm cleared when abort or retry comes. mohor 8176d 12h /ethmac/tags/rel_18/rtl/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8176d 12h /ethmac/tags/rel_18/rtl/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8176d 12h /ethmac/tags/rel_18/rtl/
58 File format changed. mohor 8176d 13h /ethmac/tags/rel_18/rtl/
57 Format of the file changed a bit. mohor 8176d 13h /ethmac/tags/rel_18/rtl/
56 File format fixed a bit. mohor 8176d 13h /ethmac/tags/rel_18/rtl/
55 Changed that were lost with last update put back to the file. mohor 8176d 13h /ethmac/tags/rel_18/rtl/
54 Addition of new module eth_addrcheck.v billditt 8177d 03h /ethmac/tags/rel_18/rtl/
53 Addition of new module eth_addrcheck.v billditt 8177d 03h /ethmac/tags/rel_18/rtl/
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8177d 04h /ethmac/tags/rel_18/rtl/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8177d 05h /ethmac/tags/rel_18/rtl/
48 RxOverRun added to statuses. mohor 8179d 07h /ethmac/tags/rel_18/rtl/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8179d 07h /ethmac/tags/rel_18/rtl/
46 HASH0 and HASH1 registers added. mohor 8179d 07h /ethmac/tags/rel_18/rtl/
43 Tx status is written back to the BD. mohor 8180d 15h /ethmac/tags/rel_18/rtl/
42 Rx status is written back to the BD. mohor 8183d 08h /ethmac/tags/rel_18/rtl/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8185d 10h /ethmac/tags/rel_18/rtl/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8186d 07h /ethmac/tags/rel_18/rtl/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8190d 11h /ethmac/tags/rel_18/rtl/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8199d 13h /ethmac/tags/rel_18/rtl/
37 Link in the header changed. mohor 8199d 14h /ethmac/tags/rel_18/rtl/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8248d 09h /ethmac/tags/rel_18/rtl/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8248d 13h /ethmac/tags/rel_18/rtl/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8248d 14h /ethmac/tags/rel_18/rtl/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8270d 10h /ethmac/tags/rel_18/rtl/
24 Log file added. mohor 8295d 13h /ethmac/tags/rel_18/rtl/
23 Number of addresses (wb_adr_i) minimized. mohor 8295d 13h /ethmac/tags/rel_18/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.