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[/] [ethmac/] [tags/] [rel_18/] [rtl/] [verilog/] - Rev 285

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Rev Log message Author Age Path
285 Binary operator used instead of unary (xnor). mohor 7668d 18h /ethmac/tags/rel_18/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7696d 19h /ethmac/tags/rel_18/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7724d 13h /ethmac/tags/rel_18/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7802d 15h /ethmac/tags/rel_18/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7802d 16h /ethmac/tags/rel_18/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7802d 16h /ethmac/tags/rel_18/rtl/verilog/
276 Defer indication changed. tadejm 7802d 16h /ethmac/tags/rel_18/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7809d 20h /ethmac/tags/rel_18/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7810d 16h /ethmac/tags/rel_18/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7811d 17h /ethmac/tags/rel_18/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7812d 17h /ethmac/tags/rel_18/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7871d 16h /ethmac/tags/rel_18/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7872d 04h /ethmac/tags/rel_18/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7873d 05h /ethmac/tags/rel_18/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7873d 05h /ethmac/tags/rel_18/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7873d 05h /ethmac/tags/rel_18/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 7873d 05h /ethmac/tags/rel_18/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7874d 11h /ethmac/tags/rel_18/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7874d 12h /ethmac/tags/rel_18/rtl/verilog/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7874d 12h /ethmac/tags/rel_18/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 7875d 12h /ethmac/tags/rel_18/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7878d 15h /ethmac/tags/rel_18/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7879d 11h /ethmac/tags/rel_18/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7880d 07h /ethmac/tags/rel_18/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7880d 07h /ethmac/tags/rel_18/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7880d 07h /ethmac/tags/rel_18/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7880d 07h /ethmac/tags/rel_18/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 7892d 11h /ethmac/tags/rel_18/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7894d 17h /ethmac/tags/rel_18/rtl/verilog/
232 fpga define added. mohor 7900d 11h /ethmac/tags/rel_18/rtl/verilog/

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