URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] - Rev 132

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	8047d 18h	/ethmac/tags/rel_19/
131	LinkFail signal was not latching appropriate bit.	mohor	8047d 19h	/ethmac/tags/rel_19/
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	8047d 19h	/ethmac/tags/rel_19/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	8047d 20h	/ethmac/tags/rel_19/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	8067d 18h	/ethmac/tags/rel_19/
126	InvalidSymbol generation changed.	mohor	8067d 19h	/ethmac/tags/rel_19/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	8067d 19h	/ethmac/tags/rel_19/
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	8067d 20h	/ethmac/tags/rel_19/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	8069d 20h	/ethmac/tags/rel_19/
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	8069d 20h	/ethmac/tags/rel_19/
120	Unused files removed.	mohor	8069d 21h	/ethmac/tags/rel_19/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	8069d 21h	/ethmac/tags/rel_19/
118	ShiftEnded synchronization changed.	mohor	8073d 12h	/ethmac/tags/rel_19/
117	Clock mrx_clk set to 2.5 MHz.	mohor	8073d 23h	/ethmac/tags/rel_19/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	8073d 23h	/ethmac/tags/rel_19/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	8074d 21h	/ethmac/tags/rel_19/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	8075d 18h	/ethmac/tags/rel_19/
113	RxPointer bug fixed.	mohor	8082d 10h	/ethmac/tags/rel_19/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	8083d 00h	/ethmac/tags/rel_19/
111	Master state machine had a bug when switching from master write to master read.	mohor	8083d 13h	/ethmac/tags/rel_19/
110	m_wb_cyc_o signal released after every single transfer.	mohor	8083d 16h	/ethmac/tags/rel_19/
109	Comment removed.	mohor	8083d 17h	/ethmac/tags/rel_19/
108	Testbench supports unaligned accesses.	mohor	8151d 03h	/ethmac/tags/rel_19/
107	TX_BUF_BASE changed.	mohor	8151d 03h	/ethmac/tags/rel_19/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8151d 03h	/ethmac/tags/rel_19/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8160d 04h	/ethmac/tags/rel_19/
104	FCS should not be included in NibbleMinFl.	mohor	8161d 22h	/ethmac/tags/rel_19/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8161d 23h	/ethmac/tags/rel_19/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8161d 23h	/ethmac/tags/rel_19/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8161d 23h	/ethmac/tags/rel_19/

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] - Rev 132

Filtering Options