OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 62

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
62 RxAbort is an output. No need to have is declared as wire. mohor 8142d 19h /ethmac/tags/rel_19/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 8142d 20h /ethmac/tags/rel_19/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8142d 20h /ethmac/tags/rel_19/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8142d 21h /ethmac/tags/rel_19/rtl/verilog/
58 File format changed. mohor 8142d 21h /ethmac/tags/rel_19/rtl/verilog/
57 Format of the file changed a bit. mohor 8142d 21h /ethmac/tags/rel_19/rtl/verilog/
56 File format fixed a bit. mohor 8142d 21h /ethmac/tags/rel_19/rtl/verilog/
55 Changed that were lost with last update put back to the file. mohor 8142d 21h /ethmac/tags/rel_19/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 8143d 11h /ethmac/tags/rel_19/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 8143d 12h /ethmac/tags/rel_19/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8143d 12h /ethmac/tags/rel_19/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8143d 13h /ethmac/tags/rel_19/rtl/verilog/
48 RxOverRun added to statuses. mohor 8145d 15h /ethmac/tags/rel_19/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8145d 15h /ethmac/tags/rel_19/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 8145d 15h /ethmac/tags/rel_19/rtl/verilog/
43 Tx status is written back to the BD. mohor 8146d 23h /ethmac/tags/rel_19/rtl/verilog/
42 Rx status is written back to the BD. mohor 8149d 16h /ethmac/tags/rel_19/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8151d 18h /ethmac/tags/rel_19/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8152d 16h /ethmac/tags/rel_19/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8156d 20h /ethmac/tags/rel_19/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8165d 22h /ethmac/tags/rel_19/rtl/verilog/
37 Link in the header changed. mohor 8165d 22h /ethmac/tags/rel_19/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8214d 17h /ethmac/tags/rel_19/rtl/verilog/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8214d 22h /ethmac/tags/rel_19/rtl/verilog/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8214d 22h /ethmac/tags/rel_19/rtl/verilog/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8236d 18h /ethmac/tags/rel_19/rtl/verilog/
24 Log file added. mohor 8261d 21h /ethmac/tags/rel_19/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8261d 21h /ethmac/tags/rel_19/rtl/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8262d 00h /ethmac/tags/rel_19/rtl/verilog/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8262d 20h /ethmac/tags/rel_19/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.