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Rev Log message Author Age Path
45 Ethernet Datasheet added. mohor 8202d 08h /ethmac/tags/rel_24/
44 Ethernet Datasheet added to cvs. mohor 8202d 08h /ethmac/tags/rel_24/
43 Tx status is written back to the BD. mohor 8203d 10h /ethmac/tags/rel_24/
42 Rx status is written back to the BD. mohor 8206d 03h /ethmac/tags/rel_24/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8208d 05h /ethmac/tags/rel_24/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8209d 02h /ethmac/tags/rel_24/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8213d 06h /ethmac/tags/rel_24/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8222d 08h /ethmac/tags/rel_24/
37 Link in the header changed. mohor 8222d 09h /ethmac/tags/rel_24/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8268d 07h /ethmac/tags/rel_24/
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8271d 04h /ethmac/tags/rel_24/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8271d 04h /ethmac/tags/rel_24/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8271d 08h /ethmac/tags/rel_24/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8271d 09h /ethmac/tags/rel_24/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8271d 09h /ethmac/tags/rel_24/
30 BD section updated. mohor 8273d 06h /ethmac/tags/rel_24/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8293d 05h /ethmac/tags/rel_24/
28 New release. Name changed to lower case. mohor 8295d 20h /ethmac/tags/rel_24/
27 File names changed to lower case. mohor 8295d 20h /ethmac/tags/rel_24/
26 First release of product brief. mohor 8295d 20h /ethmac/tags/rel_24/
25 First release of product brief. mohor 8295d 21h /ethmac/tags/rel_24/
24 Log file added. mohor 8318d 08h /ethmac/tags/rel_24/
23 Number of addresses (wb_adr_i) minimized. mohor 8318d 08h /ethmac/tags/rel_24/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8318d 10h /ethmac/tags/rel_24/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8319d 07h /ethmac/tags/rel_24/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8343d 04h /ethmac/tags/rel_24/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8343d 04h /ethmac/tags/rel_24/
18 Few little NCSIM warnings fixed. mohor 8356d 05h /ethmac/tags/rel_24/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8383d 05h /ethmac/tags/rel_24/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8390d 11h /ethmac/tags/rel_24/

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