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[/] [ethmac/] [tags/] [rel_24/] - Rev 51

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51 Added separate tests for Multicast, Unicast, Broadcast billditt 8168d 11h /ethmac/tags/rel_24/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8168d 12h /ethmac/tags/rel_24/
49 HASH0 and HASH1 register read/write added. mohor 8170d 11h /ethmac/tags/rel_24/
48 RxOverRun added to statuses. mohor 8170d 15h /ethmac/tags/rel_24/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8170d 15h /ethmac/tags/rel_24/
46 HASH0 and HASH1 registers added. mohor 8170d 15h /ethmac/tags/rel_24/
45 Ethernet Datasheet added. mohor 8170d 21h /ethmac/tags/rel_24/
44 Ethernet Datasheet added to cvs. mohor 8170d 21h /ethmac/tags/rel_24/
43 Tx status is written back to the BD. mohor 8171d 22h /ethmac/tags/rel_24/
42 Rx status is written back to the BD. mohor 8174d 15h /ethmac/tags/rel_24/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8176d 17h /ethmac/tags/rel_24/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8177d 15h /ethmac/tags/rel_24/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8181d 19h /ethmac/tags/rel_24/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8190d 21h /ethmac/tags/rel_24/
37 Link in the header changed. mohor 8190d 21h /ethmac/tags/rel_24/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8236d 19h /ethmac/tags/rel_24/
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8239d 16h /ethmac/tags/rel_24/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8239d 17h /ethmac/tags/rel_24/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8239d 21h /ethmac/tags/rel_24/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8239d 21h /ethmac/tags/rel_24/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8239d 22h /ethmac/tags/rel_24/
30 BD section updated. mohor 8241d 18h /ethmac/tags/rel_24/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8261d 17h /ethmac/tags/rel_24/
28 New release. Name changed to lower case. mohor 8264d 09h /ethmac/tags/rel_24/
27 File names changed to lower case. mohor 8264d 09h /ethmac/tags/rel_24/
26 First release of product brief. mohor 8264d 09h /ethmac/tags/rel_24/
25 First release of product brief. mohor 8264d 09h /ethmac/tags/rel_24/
24 Log file added. mohor 8286d 20h /ethmac/tags/rel_24/
23 Number of addresses (wb_adr_i) minimized. mohor 8286d 20h /ethmac/tags/rel_24/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8286d 23h /ethmac/tags/rel_24/

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