OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] - Rev 180

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
180 Bench outputs data to display every 128 bytes. mohor 7923d 05h /ethmac/tags/rel_27/
179 Beautiful tests merget together mohor 7923d 06h /ethmac/tags/rel_27/
178 Rearanged testcases mohor 7923d 06h /ethmac/tags/rel_27/
177 Bug in MIIM fixed. mohor 7923d 10h /ethmac/tags/rel_27/
176 lists changed to new directory structure mohor 7923d 11h /ethmac/tags/rel_27/
175 Script fixed to new dir structure mohor 7923d 12h /ethmac/tags/rel_27/
174 Directory keeper mohor 7923d 12h /ethmac/tags/rel_27/
173 Keeps the directory mohor 7923d 12h /ethmac/tags/rel_27/
172 NCSIM simulation environment added to cvs mohor 7923d 12h /ethmac/tags/rel_27/
171 NCSIM simulation environment added. mohor 7923d 12h /ethmac/tags/rel_27/
170 Headers changed. mohor 7923d 12h /ethmac/tags/rel_27/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7923d 13h /ethmac/tags/rel_27/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7924d 10h /ethmac/tags/rel_27/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7925d 10h /ethmac/tags/rel_27/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7926d 11h /ethmac/tags/rel_27/
165 HASH improvement needed. mohor 7926d 14h /ethmac/tags/rel_27/
164 Ethernet debug registers removed. mohor 7926d 14h /ethmac/tags/rel_27/
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7927d 06h /ethmac/tags/rel_27/
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7927d 06h /ethmac/tags/rel_27/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7927d 12h /ethmac/tags/rel_27/
160 error acknowledge cycle termination added to display. mohor 7927d 12h /ethmac/tags/rel_27/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7928d 08h /ethmac/tags/rel_27/
158 Typo fixed. mohor 7928d 08h /ethmac/tags/rel_27/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7930d 14h /ethmac/tags/rel_27/
156 Valid testbench. mohor 7930d 14h /ethmac/tags/rel_27/
155 Minor changes. mohor 7930d 14h /ethmac/tags/rel_27/
154 Design document is still under construction. mohor 7931d 13h /ethmac/tags/rel_27/
153 Temp version (backup). mohor 7932d 04h /ethmac/tags/rel_27/
152 Version 1.16 created. See revision history in the document for details. mohor 7932d 04h /ethmac/tags/rel_27/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7932d 06h /ethmac/tags/rel_27/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.