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29 Generic memory model is used. Defines are changed for the same reason. mohor 8278d 23h /ethmac/tags/rel_27/
28 New release. Name changed to lower case. mohor 8281d 15h /ethmac/tags/rel_27/
27 File names changed to lower case. mohor 8281d 15h /ethmac/tags/rel_27/
26 First release of product brief. mohor 8281d 15h /ethmac/tags/rel_27/
25 First release of product brief. mohor 8281d 15h /ethmac/tags/rel_27/
24 Log file added. mohor 8304d 02h /ethmac/tags/rel_27/
23 Number of addresses (wb_adr_i) minimized. mohor 8304d 02h /ethmac/tags/rel_27/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8304d 05h /ethmac/tags/rel_27/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8305d 02h /ethmac/tags/rel_27/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8328d 23h /ethmac/tags/rel_27/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8328d 23h /ethmac/tags/rel_27/
18 Few little NCSIM warnings fixed. mohor 8342d 00h /ethmac/tags/rel_27/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8369d 00h /ethmac/tags/rel_27/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8376d 05h /ethmac/tags/rel_27/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8377d 23h /ethmac/tags/rel_27/
14 Unconnected signals are now connected. mohor 8382d 04h /ethmac/tags/rel_27/
13 New directory structure. Files upodated and put together. mohor 8384d 13h /ethmac/tags/rel_27/
12 Directory structure changed. Files checked and joind together. mohor 8384d 16h /ethmac/tags/rel_27/
11 Directory structure changed. Files checked and joind together. mohor 8384d 16h /ethmac/tags/rel_27/
10 Directory structure changed. Files checked and joind together. mohor 8384d 16h /ethmac/tags/rel_27/
9 Documentation updated to be synchronized to the verilog files. mohor 8412d 01h /ethmac/tags/rel_27/
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8439d 06h /ethmac/tags/rel_27/
7 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8439d 06h /ethmac/tags/rel_27/
6 no message mohor 8439d 06h /ethmac/tags/rel_27/
5 This is a Microsoft version of the spec in the pdf format. mohor 8443d 15h /ethmac/tags/rel_27/
4 deleted mohor 8443d 15h /ethmac/tags/rel_27/
2 no message mohor 8515d 16h /ethmac/tags/rel_27/
1 Standard project directories initialized by cvs2svn. 8515d 16h /ethmac/tags/rel_27/

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