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[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog/] - Rev 143

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Rev	Log message	Author	Age	Path
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	7958d 22h	/ethmac/tags/rel_27/rtl/verilog/
141	Syntax error fixed.	mohor	7961d 16h	/ethmac/tags/rel_27/rtl/verilog/
140	Syntax error fixed.	mohor	7961d 16h	/ethmac/tags/rel_27/rtl/verilog/
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	7961d 16h	/ethmac/tags/rel_27/rtl/verilog/
138	Synchronous reset added.	mohor	7961d 16h	/ethmac/tags/rel_27/rtl/verilog/
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7961d 16h	/ethmac/tags/rel_27/rtl/verilog/
136	Parameter ResetValue changed to capital letters.	mohor	7962d 02h	/ethmac/tags/rel_27/rtl/verilog/
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7963d 19h	/ethmac/tags/rel_27/rtl/verilog/
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7963d 20h	/ethmac/tags/rel_27/rtl/verilog/
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7963d 20h	/ethmac/tags/rel_27/rtl/verilog/
131	LinkFail signal was not latching appropriate bit.	mohor	7963d 20h	/ethmac/tags/rel_27/rtl/verilog/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7963d 21h	/ethmac/tags/rel_27/rtl/verilog/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7983d 20h	/ethmac/tags/rel_27/rtl/verilog/
126	InvalidSymbol generation changed.	mohor	7983d 20h	/ethmac/tags/rel_27/rtl/verilog/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7983d 20h	/ethmac/tags/rel_27/rtl/verilog/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7985d 22h	/ethmac/tags/rel_27/rtl/verilog/
120	Unused files removed.	mohor	7985d 23h	/ethmac/tags/rel_27/rtl/verilog/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7985d 23h	/ethmac/tags/rel_27/rtl/verilog/
118	ShiftEnded synchronization changed.	mohor	7989d 14h	/ethmac/tags/rel_27/rtl/verilog/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7990d 22h	/ethmac/tags/rel_27/rtl/verilog/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7991d 19h	/ethmac/tags/rel_27/rtl/verilog/
113	RxPointer bug fixed.	mohor	7998d 11h	/ethmac/tags/rel_27/rtl/verilog/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7999d 01h	/ethmac/tags/rel_27/rtl/verilog/
111	Master state machine had a bug when switching from master write to master read.	mohor	7999d 14h	/ethmac/tags/rel_27/rtl/verilog/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7999d 17h	/ethmac/tags/rel_27/rtl/verilog/
109	Comment removed.	mohor	7999d 18h	/ethmac/tags/rel_27/rtl/verilog/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8067d 04h	/ethmac/tags/rel_27/rtl/verilog/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8076d 05h	/ethmac/tags/rel_27/rtl/verilog/
104	FCS should not be included in NibbleMinFl.	mohor	8077d 23h	/ethmac/tags/rel_27/rtl/verilog/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8078d 00h	/ethmac/tags/rel_27/rtl/verilog/

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[/] [ethmac/] [tags/] [rel_27/] [rtl/] [verilog/] - Rev 143

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