OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_8/] - Rev 168

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7947d 03h /ethmac/tags/rel_8/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7948d 04h /ethmac/tags/rel_8/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7949d 04h /ethmac/tags/rel_8/
165 HASH improvement needed. mohor 7949d 08h /ethmac/tags/rel_8/
164 Ethernet debug registers removed. mohor 7949d 08h /ethmac/tags/rel_8/
163 Another temporary version. Core is almost finished. Testbench not included,
yet"
mohor 7950d 00h /ethmac/tags/rel_8/
162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 7950d 00h /ethmac/tags/rel_8/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7950d 05h /ethmac/tags/rel_8/
160 error acknowledge cycle termination added to display. mohor 7950d 05h /ethmac/tags/rel_8/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7951d 02h /ethmac/tags/rel_8/
158 Typo fixed. mohor 7951d 02h /ethmac/tags/rel_8/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7953d 07h /ethmac/tags/rel_8/
156 Valid testbench. mohor 7953d 07h /ethmac/tags/rel_8/
155 Minor changes. mohor 7953d 07h /ethmac/tags/rel_8/
154 Design document is still under construction. mohor 7954d 06h /ethmac/tags/rel_8/
153 Temp version (backup). mohor 7954d 22h /ethmac/tags/rel_8/
152 Version 1.16 created. See revision history in the document for details. mohor 7954d 22h /ethmac/tags/rel_8/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7954d 23h /ethmac/tags/rel_8/
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 7955d 00h /ethmac/tags/rel_8/
148 Bug when last byte of destination address was not checked fixed. mohor 7955d 00h /ethmac/tags/rel_8/
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7955d 00h /ethmac/tags/rel_8/
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7955d 00h /ethmac/tags/rel_8/
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7955d 00h /ethmac/tags/rel_8/
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 7971d 02h /ethmac/tags/rel_8/
141 Syntax error fixed. mohor 7973d 20h /ethmac/tags/rel_8/
140 Syntax error fixed. mohor 7973d 20h /ethmac/tags/rel_8/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7973d 20h /ethmac/tags/rel_8/
138 Synchronous reset added. mohor 7973d 20h /ethmac/tags/rel_8/
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 7973d 20h /ethmac/tags/rel_8/
136 Parameter ResetValue changed to capital letters. mohor 7974d 06h /ethmac/tags/rel_8/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.