OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_9/] - Rev 125

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7991d 14h /ethmac/tags/rel_9/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7991d 15h /ethmac/tags/rel_9/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7993d 15h /ethmac/tags/rel_9/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7993d 15h /ethmac/tags/rel_9/
120 Unused files removed. mohor 7993d 17h /ethmac/tags/rel_9/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7993d 17h /ethmac/tags/rel_9/
118 ShiftEnded synchronization changed. mohor 7997d 07h /ethmac/tags/rel_9/
117 Clock mrx_clk set to 2.5 MHz. mohor 7997d 18h /ethmac/tags/rel_9/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7997d 18h /ethmac/tags/rel_9/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7998d 16h /ethmac/tags/rel_9/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7999d 13h /ethmac/tags/rel_9/
113 RxPointer bug fixed. mohor 8006d 05h /ethmac/tags/rel_9/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8006d 19h /ethmac/tags/rel_9/
111 Master state machine had a bug when switching from master write to
master read.
mohor 8007d 08h /ethmac/tags/rel_9/
110 m_wb_cyc_o signal released after every single transfer. mohor 8007d 11h /ethmac/tags/rel_9/
109 Comment removed. mohor 8007d 12h /ethmac/tags/rel_9/
108 Testbench supports unaligned accesses. mohor 8074d 22h /ethmac/tags/rel_9/
107 TX_BUF_BASE changed. mohor 8074d 22h /ethmac/tags/rel_9/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8074d 22h /ethmac/tags/rel_9/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8083d 23h /ethmac/tags/rel_9/
104 FCS should not be included in NibbleMinFl. mohor 8085d 17h /ethmac/tags/rel_9/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8085d 18h /ethmac/tags/rel_9/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8085d 18h /ethmac/tags/rel_9/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8085d 18h /ethmac/tags/rel_9/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8085d 18h /ethmac/tags/rel_9/
99 Document revised. mohor 8092d 17h /ethmac/tags/rel_9/
98 Document revised. mohor 8092d 17h /ethmac/tags/rel_9/
97 Small typo fixed. lampret 8109d 16h /ethmac/tags/rel_9/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8113d 16h /ethmac/tags/rel_9/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8113d 18h /ethmac/tags/rel_9/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.