OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_9/] [rtl/] - Rev 360

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 5500d 04h /ethmac/tags/rel_9/rtl/
335 New directory structure. root 5557d 09h /ethmac/tags/rel_9/rtl/
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7879d 06h /ethmac/tags/rel_9/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7879d 06h /ethmac/tags/rel_9/rtl/
232 fpga define added. mohor 7885d 00h /ethmac/tags/rel_9/rtl/
229 case changed to casex. mohor 7890d 22h /ethmac/tags/rel_9/rtl/
227 Changed BIST scan signals. tadejm 7891d 02h /ethmac/tags/rel_9/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7891d 04h /ethmac/tags/rel_9/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7895d 03h /ethmac/tags/rel_9/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7898d 04h /ethmac/tags/rel_9/rtl/
218 Typo error fixed. (When using Bist) mohor 7898d 06h /ethmac/tags/rel_9/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7899d 02h /ethmac/tags/rel_9/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7899d 02h /ethmac/tags/rel_9/rtl/
212 Minor $display change. mohor 7899d 03h /ethmac/tags/rel_9/rtl/
211 Bist added. mohor 7899d 03h /ethmac/tags/rel_9/rtl/
210 BIST added. mohor 7899d 03h /ethmac/tags/rel_9/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7916d 01h /ethmac/tags/rel_9/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7916d 01h /ethmac/tags/rel_9/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7919d 02h /ethmac/tags/rel_9/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7927d 04h /ethmac/tags/rel_9/rtl/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7928d 05h /ethmac/tags/rel_9/rtl/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7929d 05h /ethmac/tags/rel_9/rtl/
165 HASH improvement needed. mohor 7929d 09h /ethmac/tags/rel_9/rtl/
164 Ethernet debug registers removed. mohor 7929d 09h /ethmac/tags/rel_9/rtl/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7930d 06h /ethmac/tags/rel_9/rtl/
160 error acknowledge cycle termination added to display. mohor 7930d 06h /ethmac/tags/rel_9/rtl/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7931d 03h /ethmac/tags/rel_9/rtl/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7935d 00h /ethmac/tags/rel_9/rtl/
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7935d 01h /ethmac/tags/rel_9/rtl/
148 Bug when last byte of destination address was not checked fixed. mohor 7935d 01h /ethmac/tags/rel_9/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.