OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 55

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
55 Changed that were lost with last update put back to the file. mohor 8148d 02h /ethmac/trunk/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 8148d 16h /ethmac/trunk/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 8148d 17h /ethmac/trunk/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8148d 17h /ethmac/trunk/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8148d 18h /ethmac/trunk/rtl/verilog/
48 RxOverRun added to statuses. mohor 8150d 20h /ethmac/trunk/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8150d 20h /ethmac/trunk/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 8150d 20h /ethmac/trunk/rtl/verilog/
43 Tx status is written back to the BD. mohor 8152d 04h /ethmac/trunk/rtl/verilog/
42 Rx status is written back to the BD. mohor 8154d 21h /ethmac/trunk/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8156d 23h /ethmac/trunk/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8157d 21h /ethmac/trunk/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8162d 01h /ethmac/trunk/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8171d 03h /ethmac/trunk/rtl/verilog/
37 Link in the header changed. mohor 8171d 03h /ethmac/trunk/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8219d 22h /ethmac/trunk/rtl/verilog/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8220d 03h /ethmac/trunk/rtl/verilog/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8220d 03h /ethmac/trunk/rtl/verilog/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8241d 23h /ethmac/trunk/rtl/verilog/
24 Log file added. mohor 8267d 02h /ethmac/trunk/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8267d 02h /ethmac/trunk/rtl/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8267d 05h /ethmac/trunk/rtl/verilog/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8268d 01h /ethmac/trunk/rtl/verilog/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8291d 22h /ethmac/trunk/rtl/verilog/
18 Few little NCSIM warnings fixed. mohor 8304d 23h /ethmac/trunk/rtl/verilog/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8331d 23h /ethmac/trunk/rtl/verilog/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8339d 05h /ethmac/trunk/rtl/verilog/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8340d 23h /ethmac/trunk/rtl/verilog/
14 Unconnected signals are now connected. mohor 8345d 04h /ethmac/trunk/rtl/verilog/
10 Directory structure changed. Files checked and joind together. mohor 8347d 16h /ethmac/trunk/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.