URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 78

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
78	- BCD subtraction - scaleb function	robfinch	554d 07h	/ft816float/trunk/rtl/verilog2/
76	- adjust 9 to 7	robfinch	556d 06h	/ft816float/trunk/rtl/verilog2/
75	- add triple precision decimal float	robfinch	556d 12h	/ft816float/trunk/rtl/verilog2/
74	- added single precision combo logic only version of FMA	robfinch	664d 05h	/ft816float/trunk/rtl/verilog2/
73	- fix Karatsuba carry chain bug	robfinch	835d 06h	/ft816float/trunk/rtl/verilog2/
72	- fix: mult32x32 prod high order bits	robfinch	835d 08h	/ft816float/trunk/rtl/verilog2/
71	- added decimal float reciprocal estimate	robfinch	843d 05h	/ft816float/trunk/rtl/verilog2/
70	- fix carry out for BCD add / sub	robfinch	843d 11h	/ft816float/trunk/rtl/verilog2/
68	- added decimal float compare	robfinch	847d 10h	/ft816float/trunk/rtl/verilog2/
67	- adding decimal float divide	robfinch	847d 14h	/ft816float/trunk/rtl/verilog2/
66	- BCD arith additions	robfinch	847d 16h	/ft816float/trunk/rtl/verilog2/
65	-update dfdiv / dfmul	robfinch	847d 16h	/ft816float/trunk/rtl/verilog2/
64	- add multiply 128 - fix exponent bias	robfinch	847d 16h	/ft816float/trunk/rtl/verilog2/
62	- fix overflow status - license comment	robfinch	848d 05h	/ft816float/trunk/rtl/verilog2/
60	- decimal float <-> int converters	robfinch	848d 07h	/ft816float/trunk/rtl/verilog2/
59	- bin to bcd and bcd to bin converters	robfinch	848d 11h	/ft816float/trunk/rtl/verilog2/
58	- generic redor	robfinch	1109d 16h	/ft816float/trunk/rtl/verilog2/
57	- decimal floating-point IEEE format encode/decode	robfinch	1251d 05h	/ft816float/trunk/rtl/verilog2/
56	- decimal square root function	robfinch	1276d 05h	/ft816float/trunk/rtl/verilog2/
55	- add storage format - parameterization	robfinch	1276d 22h	/ft816float/trunk/rtl/verilog2/
54	- add decimal float divider	robfinch	1277d 11h	/ft816float/trunk/rtl/verilog2/
53	- added decimal floating-point multiplier	robfinch	1278d 15h	/ft816float/trunk/rtl/verilog2/
51	- got rid of 'DF0'	robfinch	1278d 18h	/ft816float/trunk/rtl/verilog2/
50	- added decimal floating-point adder	robfinch	1279d 02h	/ft816float/trunk/rtl/verilog2/
49	- pipelining	robfinch	1299d 07h	/ft816float/trunk/rtl/verilog2/
48	- refactoring to use packages	robfinch	1323d 15h	/ft816float/trunk/rtl/verilog2/
35	- additional pipelining in divider - radix4 primitive	robfinch	1539d 05h	/ft816float/trunk/rtl/verilog2/
34	- add pipeline stage in divider	robfinch	1539d 08h	/ft816float/trunk/rtl/verilog2/
33	- mult114 for FMA	robfinch	1791d 16h	/ft816float/trunk/rtl/verilog2/
32	- FMA, test bench for FMA	robfinch	1791d 16h	/ft816float/trunk/rtl/verilog2/

Browse

Tools

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 78

Filtering Options