OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 80

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
80 - improve decimal float divide robfinch 560d 14h /ft816float/trunk/rtl/verilog2/
79 - fix sticky infinity robfinch 561d 22h /ft816float/trunk/rtl/verilog2/
78 - BCD subtraction
- scaleb function		 robfinch 562d 10h /ft816float/trunk/rtl/verilog2/
76 - adjust 9 to 7 robfinch 564d 10h /ft816float/trunk/rtl/verilog2/
75 - add triple precision decimal float robfinch 564d 15h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 672d 09h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 843d 09h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 843d 11h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 851d 08h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 851d 15h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 855d 13h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 855d 17h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 855d 19h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 855d 19h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 855d 19h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 856d 08h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 856d 10h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 856d 14h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1117d 19h /ft816float/trunk/rtl/verilog2/
57 - decimal floating-point IEEE format encode/decode robfinch 1259d 08h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1284d 08h /ft816float/trunk/rtl/verilog2/
55 - add storage format
- parameterization		 robfinch 1285d 01h /ft816float/trunk/rtl/verilog2/
54 - add decimal float divider robfinch 1285d 14h /ft816float/trunk/rtl/verilog2/
53 - added decimal floating-point multiplier robfinch 1286d 19h /ft816float/trunk/rtl/verilog2/
51 - got rid of 'DF0' robfinch 1286d 21h /ft816float/trunk/rtl/verilog2/
50 - added decimal floating-point adder robfinch 1287d 05h /ft816float/trunk/rtl/verilog2/
49 - pipelining robfinch 1307d 10h /ft816float/trunk/rtl/verilog2/
48 - refactoring to use packages robfinch 1331d 18h /ft816float/trunk/rtl/verilog2/
35 - additional pipelining in divider
- radix4 primitive		 robfinch 1547d 08h /ft816float/trunk/rtl/verilog2/
34 - add pipeline stage in divider robfinch 1547d 11h /ft816float/trunk/rtl/verilog2/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.