Rev |
Log message |
Author |
Age |
Path |
51 |
Making test case pass for SOPC simulation. |
edn_walter |
4479d 02h |
/ha1588/ |
50 |
Added missing simulation library. |
edn_walter |
4479d 02h |
/ha1588/ |
49 |
Added missing simulation library. |
edn_walter |
4479d 11h |
/ha1588/ |
48 |
1. Added testbench for SOPC Builder example. Need to fully implement the self-check test cases. Just ignore the reported failures, and check the waveform for correct addressing.
2. Added GENERATE BLOCK for top-level addr_in unit selection. In normal top-level instantiation without modify the default addr_is_in_word = 0 parameter, the default address unit is in byte (8bit); When instantiated in SOPC Builder, the address unit is default to word (32bit). |
edn_walter |
4479d 15h |
/ha1588/ |
47 |
Added test case of -16 negative period_adj value, to show the effect trying to set time backwards. Thanks to Frank Yang's question. |
edn_walter |
4480d 02h |
/ha1588/ |
46 |
Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. |
edn_walter |
4482d 17h |
/ha1588/ |
45 |
1. optimized area, by removing unused registers.
2. optimized timing, by removing latches. |
edn_walter |
4483d 08h |
/ha1588/ |
44 |
Updated TSU testbench. |
edn_walter |
4483d 11h |
/ha1588/ |
43 |
Added software configurable PTP message id mask for TSU parser. |
edn_walter |
4484d 09h |
/ha1588/ |
42 |
Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. |
edn_walter |
4484d 15h |
/ha1588/ |
41 |
Added pre-adder to the accumulator to cut down critical timing path. |
edn_walter |
4484d 16h |
/ha1588/ |
40 |
Release version 1.1 |
edn_walter |
4484d 20h |
/ha1588/ |
39 |
1. Added memory map and feature description.
2. Separated TX RX TSU register addresses. |
edn_walter |
4484d 20h |
/ha1588/ |
38 |
1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side. |
edn_walter |
4485d 18h |
/ha1588/ |
37 |
Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit |
edn_walter |
4485d 21h |
/ha1588/ |
36 |
TSU testbench is now self-checking. Test result is reported at end of simulation. |
edn_walter |
4486d 16h |
/ha1588/ |
35 |
Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. |
edn_walter |
4487d 15h |
/ha1588/ |
34 |
Added LGPL file header to all copyrighted files. |
edn_walter |
4487d 18h |
/ha1588/ |
33 |
Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. |
edn_walter |
4487d 19h |
/ha1588/ |
32 |
Added PTP standard time format output to the top module. Can be connected to external modules. |
edn_walter |
4487d 21h |
/ha1588/ |
31 |
Added hand-shaking for the TSU data reading. |
edn_walter |
4488d 15h |
/ha1588/ |
30 |
Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit |
edn_walter |
4488d 15h |
/ha1588/ |
29 |
Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. |
edn_walter |
4488d 15h |
/ha1588/ |
28 |
Before changing TSU packet parser datapath width from 32b to 8b. |
edn_walter |
4488d 21h |
/ha1588/ |
27 |
Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. |
edn_walter |
4488d 21h |
/ha1588/ |
26 |
Updated test case. |
edn_walter |
4490d 16h |
/ha1588/ |
25 |
Updated SOPC Builder component and example system. |
edn_walter |
4491d 15h |
/ha1588/ |
24 |
Added test cases for top-level testbench to cover both RTC and TSU. |
edn_walter |
4491d 17h |
/ha1588/ |
23 |
Added CDC hand-shaking for RTC time reading operation. |
edn_walter |
4492d 11h |
/ha1588/ |
22 |
RTC reset will clear ACC counter, but not clear ACC counter incremental. |
edn_walter |
4492d 15h |
/ha1588/ |