| Rev |
Log message |
Author |
Age |
Path |
| 53 |
Corrected 2 bugs: SOPC addressing and Wrong Preamble+SFD format. |
edn_walter |
4488d 22h |
/ha1588/tags/v1p2/sim/ |
| 52 |
1. Corrected GMII BFM preamble+sfd size error: 4B 5555555d changed to 8B 5555555555555555d5.
2. Corrected packet parser 4B counter accordingly. |
edn_walter |
4488d 22h |
/ha1588/trunk/sim/ |
| 51 |
Making test case pass for SOPC simulation. |
edn_walter |
4493d 09h |
/ha1588/trunk/sim/ |
| 50 |
Added missing simulation library. |
edn_walter |
4493d 09h |
/ha1588/trunk/sim/ |
| 49 |
Added missing simulation library. |
edn_walter |
4493d 18h |
/ha1588/trunk/sim/ |
| 48 |
1. Added testbench for SOPC Builder example. Need to fully implement the self-check test cases. Just ignore the reported failures, and check the waveform for correct addressing.
2. Added GENERATE BLOCK for top-level addr_in unit selection. In normal top-level instantiation without modify the default addr_is_in_word = 0 parameter, the default address unit is in byte (8bit); When instantiated in SOPC Builder, the address unit is default to word (32bit). |
edn_walter |
4493d 22h |
/ha1588/trunk/sim/ |
| 47 |
Added test case of -16 negative period_adj value, to show the effect trying to set time backwards. Thanks to Frank Yang's question. |
edn_walter |
4494d 08h |
/ha1588/trunk/sim/ |
| 46 |
Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. |
edn_walter |
4497d 00h |
/ha1588/trunk/sim/ |
| 44 |
Updated TSU testbench. |
edn_walter |
4497d 18h |
/ha1588/trunk/sim/ |
| 43 |
Added software configurable PTP message id mask for TSU parser. |
edn_walter |
4498d 15h |
/ha1588/trunk/sim/ |
| 42 |
Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. |
edn_walter |
4498d 21h |
/ha1588/trunk/sim/ |
| 41 |
Added pre-adder to the accumulator to cut down critical timing path. |
edn_walter |
4498d 23h |
/ha1588/trunk/sim/ |
| 39 |
1. Added memory map and feature description.
2. Separated TX RX TSU register addresses. |
edn_walter |
4499d 03h |
/ha1588/trunk/sim/ |
| 38 |
1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side. |
edn_walter |
4500d 00h |
/ha1588/trunk/sim/ |
| 37 |
Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit |
edn_walter |
4500d 04h |
/ha1588/trunk/sim/ |
| 36 |
TSU testbench is now self-checking. Test result is reported at end of simulation. |
edn_walter |
4500d 23h |
/ha1588/trunk/sim/ |
| 35 |
Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. |
edn_walter |
4501d 22h |
/ha1588/trunk/sim/ |
| 34 |
Added LGPL file header to all copyrighted files. |
edn_walter |
4502d 00h |
/ha1588/trunk/sim/ |
| 33 |
Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. |
edn_walter |
4502d 02h |
/ha1588/trunk/sim/ |
| 32 |
Added PTP standard time format output to the top module. Can be connected to external modules. |
edn_walter |
4502d 04h |
/ha1588/trunk/sim/ |
| 31 |
Added hand-shaking for the TSU data reading. |
edn_walter |
4502d 22h |
/ha1588/trunk/sim/ |
| 30 |
Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit |
edn_walter |
4502d 22h |
/ha1588/trunk/sim/ |
| 29 |
Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. |
edn_walter |
4502d 22h |
/ha1588/trunk/sim/ |
| 26 |
Updated test case. |
edn_walter |
4504d 23h |
/ha1588/trunk/sim/ |
| 24 |
Added test cases for top-level testbench to cover both RTC and TSU. |
edn_walter |
4505d 23h |
/ha1588/trunk/sim/ |
| 23 |
Added CDC hand-shaking for RTC time reading operation. |
edn_walter |
4506d 17h |
/ha1588/trunk/sim/ |
| 22 |
RTC reset will clear ACC counter, but not clear ACC counter incremental. |
edn_walter |
4506d 21h |
/ha1588/trunk/sim/ |
| 21 |
Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. |
edn_walter |
4507d 18h |
/ha1588/trunk/sim/ |
| 19 |
Added pipeline registers to Real Time Clock module to improve timing. |
edn_walter |
4511d 22h |
/ha1588/trunk/sim/ |
| 15 |
Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component. |
edn_walter |
4518d 18h |
/ha1588/trunk/sim/ |
