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[/] [ha1588/] [trunk/] - Rev 34

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34 Added LGPL file header to all copyrighted files. edn_walter 4520d 22h /ha1588/trunk/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4521d 00h /ha1588/trunk/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4521d 02h /ha1588/trunk/
31 Added hand-shaking for the TSU data reading. edn_walter 4521d 19h /ha1588/trunk/
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4521d 19h /ha1588/trunk/
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4521d 20h /ha1588/trunk/
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4522d 02h /ha1588/trunk/
26 Updated test case. edn_walter 4523d 21h /ha1588/trunk/
25 Updated SOPC Builder component and example system. edn_walter 4524d 20h /ha1588/trunk/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4524d 21h /ha1588/trunk/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4525d 15h /ha1588/trunk/
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4525d 19h /ha1588/trunk/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4526d 16h /ha1588/trunk/
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 4530d 20h /ha1588/trunk/
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4530d 20h /ha1588/trunk/
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4530d 20h /ha1588/trunk/
17 Updated reg.v content. edn_walter 4531d 14h /ha1588/trunk/
16 Try to add sth. edn_walter 4535d 07h /ha1588/trunk/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4537d 15h /ha1588/trunk/
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 4539d 15h /ha1588/trunk/
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 4540d 15h /ha1588/trunk/
12 Added parser support for vlan tagged frames. edn_walter 4541d 14h /ha1588/trunk/
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 4542d 15h /ha1588/trunk/
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 4543d 15h /ha1588/trunk/
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 4544d 15h /ha1588/trunk/
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 4544d 22h /ha1588/trunk/
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 4544d 22h /ha1588/trunk/
6 Reduced the size of the Vendor specific simulation library file. ash_riple 4546d 22h /ha1588/trunk/
5 Added dcfifo to store ptp time stamps. ash_riple 4547d 14h /ha1588/trunk/
4 Added source code and unit test for TSU. ash_riple 4548d 14h /ha1588/trunk/

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