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[/] [ha1588/] [trunk/] [sim/] - Rev 36

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36 TSU testbench is now self-checking. Test result is reported at end of simulation. edn_walter 4495d 19h /ha1588/trunk/sim/
35 Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. edn_walter 4496d 18h /ha1588/trunk/sim/
34 Added LGPL file header to all copyrighted files. edn_walter 4496d 21h /ha1588/trunk/sim/
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4496d 22h /ha1588/trunk/sim/
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4497d 00h /ha1588/trunk/sim/
31 Added hand-shaking for the TSU data reading. edn_walter 4497d 18h /ha1588/trunk/sim/
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4497d 18h /ha1588/trunk/sim/
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4497d 18h /ha1588/trunk/sim/
26 Updated test case. edn_walter 4499d 19h /ha1588/trunk/sim/
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4500d 20h /ha1588/trunk/sim/
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4501d 14h /ha1588/trunk/sim/
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4501d 18h /ha1588/trunk/sim/
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4502d 14h /ha1588/trunk/sim/
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4506d 19h /ha1588/trunk/sim/
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4513d 14h /ha1588/trunk/sim/
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 4515d 14h /ha1588/trunk/sim/
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 4516d 14h /ha1588/trunk/sim/
12 Added parser support for vlan tagged frames. edn_walter 4517d 12h /ha1588/trunk/sim/
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 4518d 14h /ha1588/trunk/sim/
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 4519d 14h /ha1588/trunk/sim/
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 4520d 13h /ha1588/trunk/sim/
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 4520d 20h /ha1588/trunk/sim/
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 4520d 21h /ha1588/trunk/sim/
6 Reduced the size of the Vendor specific simulation library file. ash_riple 4522d 21h /ha1588/trunk/sim/
5 Added dcfifo to store ptp time stamps. ash_riple 4523d 12h /ha1588/trunk/sim/
4 Added source code and unit test for TSU. ash_riple 4524d 13h /ha1588/trunk/sim/
3 Added function block RTC and its unit test. ash_riple 4531d 13h /ha1588/trunk/sim/

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