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[/] [i2c/] [tags/] [asyst_2/] - Rev 22

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Rev Log message Author Age Path
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8030d 03h /i2c/tags/asyst_2/
21 no message rherveille 8116d 04h /i2c/tags/asyst_2/
20 Added Appendix A rherveille 8116d 04h /i2c/tags/asyst_2/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8120d 00h /i2c/tags/asyst_2/
18 no message rherveille 8146d 20h /i2c/tags/asyst_2/
17 C-include file.
Initial release		 rherveille 8235d 01h /i2c/tags/asyst_2/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8247d 00h /i2c/tags/asyst_2/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8251d 23h /i2c/tags/asyst_2/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8251d 23h /i2c/tags/asyst_2/
13 Fixed some synthesis warnings. rherveille 8263d 03h /i2c/tags/asyst_2/
12 no message rherveille 8268d 18h /i2c/tags/asyst_2/
11 Changed RST_LVL define to parameter. rherveille 8272d 02h /i2c/tags/asyst_2/
10 Created new directory structure.
Added Verilog version.		 rherveille 8293d 22h /i2c/tags/asyst_2/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8363d 17h /i2c/tags/asyst_2/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8363d 17h /i2c/tags/asyst_2/
7 added some remarks, fixed some sensitivity lists rherveille 8432d 20h /i2c/tags/asyst_2/
6 fixed typo txt -> txr rherveille 8437d 00h /i2c/tags/asyst_2/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8443d 22h /i2c/tags/asyst_2/
4 WISHBONE I2C Master Core: initial release rherveille 8496d 01h /i2c/tags/asyst_2/
2 initial release rherveille 8558d 01h /i2c/tags/asyst_2/
1 Standard project directories initialized by cvs2svn. 8558d 01h /i2c/tags/asyst_2/

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