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[/] [i2c/] [tags/] [asyst_3/] - Rev 31

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Rev Log message Author Age Path
31 Core is now a Multimaster I2C controller. rherveille 7824d 19h /i2c/tags/asyst_3/
30 Small code simplifications rherveille 7824d 19h /i2c/tags/asyst_3/
29 Core is now a Multimaster I2C controller rherveille 7824d 20h /i2c/tags/asyst_3/
28 *** empty log message *** rherveille 7850d 12h /i2c/tags/asyst_3/
27 Cleaned up code rherveille 7850d 12h /i2c/tags/asyst_3/
26 *** empty log message *** rherveille 7853d 20h /i2c/tags/asyst_3/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7881d 17h /i2c/tags/asyst_3/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7881d 17h /i2c/tags/asyst_3/
23 *** empty log message *** rherveille 8008d 22h /i2c/tags/asyst_3/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8019d 03h /i2c/tags/asyst_3/
21 no message rherveille 8105d 04h /i2c/tags/asyst_3/
20 Added Appendix A rherveille 8105d 04h /i2c/tags/asyst_3/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8109d 00h /i2c/tags/asyst_3/
18 no message rherveille 8135d 20h /i2c/tags/asyst_3/
17 C-include file.
Initial release		 rherveille 8224d 01h /i2c/tags/asyst_3/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8236d 00h /i2c/tags/asyst_3/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8240d 23h /i2c/tags/asyst_3/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8240d 23h /i2c/tags/asyst_3/
13 Fixed some synthesis warnings. rherveille 8252d 03h /i2c/tags/asyst_3/
12 no message rherveille 8257d 18h /i2c/tags/asyst_3/
11 Changed RST_LVL define to parameter. rherveille 8261d 02h /i2c/tags/asyst_3/
10 Created new directory structure.
Added Verilog version.		 rherveille 8282d 22h /i2c/tags/asyst_3/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8352d 17h /i2c/tags/asyst_3/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8352d 18h /i2c/tags/asyst_3/
7 added some remarks, fixed some sensitivity lists rherveille 8421d 20h /i2c/tags/asyst_3/
6 fixed typo txt -> txr rherveille 8426d 00h /i2c/tags/asyst_3/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8432d 22h /i2c/tags/asyst_3/
4 WISHBONE I2C Master Core: initial release rherveille 8485d 01h /i2c/tags/asyst_3/
2 initial release rherveille 8547d 01h /i2c/tags/asyst_3/
1 Standard project directories initialized by cvs2svn. 8547d 01h /i2c/tags/asyst_3/

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