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[/] [i2c/] [tags/] [rel_1/] - Rev 31

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Rev Log message Author Age Path
31 Core is now a Multimaster I2C controller. rherveille 7847d 20h /i2c/tags/rel_1/
30 Small code simplifications rherveille 7847d 20h /i2c/tags/rel_1/
29 Core is now a Multimaster I2C controller rherveille 7847d 21h /i2c/tags/rel_1/
28 *** empty log message *** rherveille 7873d 14h /i2c/tags/rel_1/
27 Cleaned up code rherveille 7873d 14h /i2c/tags/rel_1/
26 *** empty log message *** rherveille 7876d 22h /i2c/tags/rel_1/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7904d 18h /i2c/tags/rel_1/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7904d 18h /i2c/tags/rel_1/
23 *** empty log message *** rherveille 8031d 23h /i2c/tags/rel_1/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8042d 05h /i2c/tags/rel_1/
21 no message rherveille 8128d 05h /i2c/tags/rel_1/
20 Added Appendix A rherveille 8128d 05h /i2c/tags/rel_1/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8132d 02h /i2c/tags/rel_1/
18 no message rherveille 8158d 22h /i2c/tags/rel_1/
17 C-include file.
Initial release		 rherveille 8247d 02h /i2c/tags/rel_1/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8259d 01h /i2c/tags/rel_1/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8264d 00h /i2c/tags/rel_1/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8264d 00h /i2c/tags/rel_1/
13 Fixed some synthesis warnings. rherveille 8275d 04h /i2c/tags/rel_1/
12 no message rherveille 8280d 20h /i2c/tags/rel_1/
11 Changed RST_LVL define to parameter. rherveille 8284d 03h /i2c/tags/rel_1/
10 Created new directory structure.
Added Verilog version.		 rherveille 8306d 00h /i2c/tags/rel_1/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8375d 19h /i2c/tags/rel_1/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8375d 19h /i2c/tags/rel_1/
7 added some remarks, fixed some sensitivity lists rherveille 8444d 22h /i2c/tags/rel_1/
6 fixed typo txt -> txr rherveille 8449d 01h /i2c/tags/rel_1/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8456d 00h /i2c/tags/rel_1/
4 WISHBONE I2C Master Core: initial release rherveille 8508d 03h /i2c/tags/rel_1/
2 initial release rherveille 8570d 02h /i2c/tags/rel_1/
1 Standard project directories initialized by cvs2svn. 8570d 02h /i2c/tags/rel_1/

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