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[/] [i2c/] [trunk/] - Rev 30

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Rev Log message Author Age Path
30 Small code simplifications rherveille 7829d 05h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7829d 06h /i2c/trunk/
28 *** empty log message *** rherveille 7854d 23h /i2c/trunk/
27 Cleaned up code rherveille 7854d 23h /i2c/trunk/
26 *** empty log message *** rherveille 7858d 07h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7886d 03h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7886d 03h /i2c/trunk/
23 *** empty log message *** rherveille 8013d 09h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8023d 14h /i2c/trunk/
21 no message rherveille 8109d 14h /i2c/trunk/
20 Added Appendix A rherveille 8109d 14h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8113d 11h /i2c/trunk/
18 no message rherveille 8140d 07h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8228d 11h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8240d 10h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8245d 09h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8245d 09h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8256d 13h /i2c/trunk/
12 no message rherveille 8262d 05h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 8265d 12h /i2c/trunk/
10 Created new directory structure.
Added Verilog version.		 rherveille 8287d 09h /i2c/trunk/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8357d 04h /i2c/trunk/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8357d 04h /i2c/trunk/
7 added some remarks, fixed some sensitivity lists rherveille 8426d 07h /i2c/trunk/
6 fixed typo txt -> txr rherveille 8430d 11h /i2c/trunk/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8437d 09h /i2c/trunk/
4 WISHBONE I2C Master Core: initial release rherveille 8489d 12h /i2c/trunk/
2 initial release rherveille 8551d 11h /i2c/trunk/
1 Standard project directories initialized by cvs2svn. 8551d 11h /i2c/trunk/

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