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[/] [i2c/] [trunk/] - Rev 51

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Rev Log message Author Age Path
51 Fixed simulation issue when writing to CR register rherveille 7404d 11h /i2c/trunk/
50 *** empty log message *** rherveille 7419d 05h /i2c/trunk/
49 Added testbench rherveille 7419d 06h /i2c/trunk/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7420d 13h /i2c/trunk/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7429d 09h /i2c/trunk/
46 Fixed slave address MSB='1' bug rherveille 7504d 10h /i2c/trunk/
45 Added slave address configurability rherveille 7504d 10h /i2c/trunk/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7589d 13h /i2c/trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7599d 11h /i2c/trunk/
39 Forgot an 'end if' :-/ rherveille 7619d 06h /i2c/trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7622d 14h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7659d 06h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7774d 07h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7807d 21h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7811d 19h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7834d 04h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7844d 04h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7848d 05h /i2c/trunk/
30 Small code simplifications rherveille 7848d 05h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7848d 06h /i2c/trunk/
28 *** empty log message *** rherveille 7873d 23h /i2c/trunk/
27 Cleaned up code rherveille 7873d 23h /i2c/trunk/
26 *** empty log message *** rherveille 7877d 07h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7905d 03h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7905d 03h /i2c/trunk/
23 *** empty log message *** rherveille 8032d 08h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8042d 13h /i2c/trunk/
21 no message rherveille 8128d 14h /i2c/trunk/
20 Added Appendix A rherveille 8128d 14h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8132d 11h /i2c/trunk/

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