URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] - Rev 120

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Rev	Log message	Author	Age	Path
120	Updated main package with lots of wait states for all areas	ja_rd	4854d 04h	/ion/
119	Updated pre-generated simulation and synthesis demos	ja_rd	4854d 04h	/ion/
118	Updates sim scripts to include new cache	ja_rd	4854d 04h	/ion/
117	Updated project doc (still not fully up to date)	ja_rd	4854d 04h	/ion/
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	4854d 05h	/ion/
115	Updated Altera CSV file (pin location file) for DE-1 board (Added 27MHz clock input)	ja_rd	4854d 07h	/ion/
114	ADDED: 1st version of real cache	ja_rd	4854d 07h	/ion/
113	Added clock frequency generic to MPU module template (the generics are used by UART submodules)	ja_rd	4854d 09h	/ion/
112	Updated simulation package for compatibility to new cache	ja_rd	4854d 09h	/ion/
111	Updated 'hello' code sample: - Longer simulated time for compatibility to new cache	ja_rd	4854d 09h	/ion/
110	Updated 'opcodes' code sample: - Longer simulated time for compatibility to new cache	ja_rd	4854d 09h	/ion/
109	Updated memtest code sample: - Initializes I-cache - Tests execution from FLASH - Uses small memory model for faster simulation	ja_rd	4854d 09h	/ion/
108	Added new 'small' memory map to SW simulator (so that memtest simulations can be shorter)	ja_rd	4854d 09h	/ion/
107	Adventure demo bootstrap code updated: - typo fixed - added basic I-cache initialization code	ja_rd	4858d 07h	/ion/
106	SW samples updated: - Added batch files for running the SW simulation	ja_rd	4858d 08h	/ion/
105	SW simulator updated: - New command line options - New optional memory map - Runs on batch mode - Other features for running uClinux	ja_rd	4858d 08h	/ion/
104	FIXED typo in last commit for simulation template	ja_rd	4862d 23h	/ion/
103	ADDED cache control inputs (unused) to dummy cache	ja_rd	4862d 23h	/ion/
102	ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4862d 23h	/ion/
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4862d 23h	/ion/
100	Obsolete synthesizable template files removed	ja_rd	4887d 09h	/ion/
99	Obsolete TB template files removed	ja_rd	4887d 09h	/ion/
98	CPU rd and wr data address buses unified	ja_rd	4887d 09h	/ion/
97	CPU rd and wr data address buses unified	ja_rd	4887d 09h	/ion/
96	CPU rd and wr data address buses unified	ja_rd	4887d 09h	/ion/
95	BUG FIX: cache stub properly handles all kind of cycles now	ja_rd	4898d 05h	/ion/
94	Pregenerated demo 'hello' files updated	ja_rd	4898d 05h	/ion/
93	SW simulator supports 'log trigger address' and keyboard input as simulated UART RX. Project parameters now launch adventure demo automatically	ja_rd	4898d 05h	/ion/
92	'hello' demo updated to use new startup files	ja_rd	4898d 05h	/ion/
91	FIX: startup files can now be used to run from FLASH or BRAM	ja_rd	4898d 05h	/ion/

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Subversion Repositories ion

[/] [ion/] - Rev 120

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