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Rev Log message Author Age Path
148 Added optional cache support to 'opcodes' test.
Updated simulation length accordingly.		 ja_rd 4844d 04h /ion/
147 SW simulator updated to latest HW revision
(plus a few mistakes corrected: wrongly commented out lines, mostly)		 ja_rd 4844d 04h /ion/
146 Added D-Cache setup code to 'adventure' bootstrap code
(redundant since common C startup code already does it but...)		 ja_rd 4844d 04h /ion/
145 MAJOR UPDATE: first version of D-Cache ja_rd 4844d 05h /ion/
144 Added cache setup code to common startup code
Important: the new cache won't work without this		 ja_rd 4844d 05h /ion/
143 'adventure' sample by default will log from 0xb0000000
and simulation length is now longer		 ja_rd 4845d 18h /ion/
142 'Adventure' bootstrap code now enables the cache
(and runs noticeably faster on DE-1 board)		 ja_rd 4845d 18h /ion/
141 BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled		 ja_rd 4845d 18h /ion/
140 BUG FIX in cpu: MTCx was using Rs as source instead of Rt
BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong		 ja_rd 4845d 19h /ion/
139 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4846d 12h /ion/
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4846d 12h /ion/
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4846d 12h /ion/
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4846d 12h /ion/
135 Added debug output to synthesizable MPU template. ja_rd 4846d 12h /ion/
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4846d 12h /ion/
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4849d 10h /ion/
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4849d 10h /ion/
131 change to local system-dependent directory path ja_rd 4849d 10h /ion/
130 typo fix ja_rd 4849d 10h /ion/
129 updated pregenerated demo ('hello') ja_rd 4849d 10h /ion/
128 updated precompiled simulation testbench ja_rd 4849d 10h /ion/
127 added SDRAM verilog simulation model to sim script ja_rd 4849d 10h /ion/
126 added SDRAM verilog simulation model ja_rd 4849d 10h /ion/
125 MPU templates now use the real cache by default ja_rd 4849d 10h /ion/
124 Fixed typo in python script header comment ja_rd 4894d 16h /ion/
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4894d 19h /ion/
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4894d 19h /ion/
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4895d 10h /ion/
120 Updated main package with lots of wait states for all areas ja_rd 4904d 13h /ion/
119 Updated pre-generated simulation and synthesis demos ja_rd 4904d 13h /ion/

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