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[/] [ion/] [trunk/] - Rev 136

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Rev Log message Author Age Path
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4778d 06h /ion/trunk/
135 Added debug output to synthesizable MPU template. ja_rd 4778d 06h /ion/trunk/
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4778d 06h /ion/trunk/
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4781d 03h /ion/trunk/
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4781d 03h /ion/trunk/
131 change to local system-dependent directory path ja_rd 4781d 04h /ion/trunk/
130 typo fix ja_rd 4781d 04h /ion/trunk/
129 updated pregenerated demo ('hello') ja_rd 4781d 04h /ion/trunk/
128 updated precompiled simulation testbench ja_rd 4781d 04h /ion/trunk/
127 added SDRAM verilog simulation model to sim script ja_rd 4781d 04h /ion/trunk/
126 added SDRAM verilog simulation model ja_rd 4781d 04h /ion/trunk/
125 MPU templates now use the real cache by default ja_rd 4781d 04h /ion/trunk/
124 Fixed typo in python script header comment ja_rd 4826d 09h /ion/trunk/
123 Added target to 'hello' makefile for cache-less system simulation ja_rd 4826d 12h /ion/trunk/
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4826d 12h /ion/trunk/
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4827d 04h /ion/trunk/
120 Updated main package with lots of wait states for all areas ja_rd 4836d 06h /ion/trunk/
119 Updated pre-generated simulation and synthesis demos ja_rd 4836d 06h /ion/trunk/
118 Updates sim scripts to include new cache ja_rd 4836d 06h /ion/trunk/
117 Updated project doc (still not fully up to date) ja_rd 4836d 07h /ion/trunk/
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic		 ja_rd 4836d 07h /ion/trunk/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)		 ja_rd 4836d 09h /ion/trunk/
114 ADDED: 1st version of real cache ja_rd 4836d 10h /ion/trunk/
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)		 ja_rd 4836d 11h /ion/trunk/
112 Updated simulation package for compatibility to new cache ja_rd 4836d 11h /ion/trunk/
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4836d 11h /ion/trunk/
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4836d 11h /ion/trunk/
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation		 ja_rd 4836d 11h /ion/trunk/
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)		 ja_rd 4836d 12h /ion/trunk/
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code		 ja_rd 4840d 10h /ion/trunk/

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